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Section Five Function Introduction to IC
3.5.1 Function introduction to HY57V641620E
1. Description
The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally
suited for the memory applications which require wide data I/O and high bandwidth. HY57V641620E
(L/S)T(P) is organized as 4banks of 1,048,576x16.
HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the
clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are
internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with
LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of
consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page),
and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be
terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write
command on any cycle. (This pipelined design is not restricted by a '2N' rule).
2. Features
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Voltage : VDD, VDDQ 3.3V supply voltage
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All device pins are compatible with LVTTL interface
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54 Pin TSOPII (Lead or Lead Free Package)
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All inputs and outputs referenced to positive edge of system clock
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Data mask function by UDQM, LDQM
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Internal four banks operation
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Auto refresh and self refresh
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4096 Refresh cycles / 64ms
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Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
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Programmable /CAS Latency ; 2, 3 Clocks
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Burst Read Single Write operation
