BIOS settings
CB1067
86
Version: 1.0
BIOS entry
Options
PCI Express Root Port 1
Disabled / Enabled
Disable Gen2 Pll Shutdown and L1 and
Controller Power gating
Disabled / Enabled
Connection type
Built-in / Slot
Gen3 Eq Phase3 Method
Hardware / Static Coeff.
UPTP
None
DPTP
None
ACS
Enabled / Disabled
PTM
Enabled / Disabled
DPC
Enabled / Disabled
EDPC
Enabled / Disabled
URR
Disabled / Enabled
FER
Disabled / Enabled
NFER
Disabled / Enabled
CER
Disabled / Enabled
CTO
Disabled / Enabled
SEFE
Disabled / Enabled
SENFE
Disabled / Enabled
PME SCI
Enabled / Disabled
Hot Plug
Disabled / Enabled
Advanced Error Reporting
Enabled / Disabled
PCIe Speed
Auto / Gen1 / Gen2 / Gen3
Transmitter Half Swing
Disabled / Enabled
Detect Timeout
None
Extra Bus Reserved
None
Reserved Memory
None
Reserved I/O
None
PCH PCIe LTR Configuration
LTR
Enabled / Disabled
Snoop Latency Override
Disabled / Manual / Auto
Non Snoop Latency Override
Disabled / Manual / Auto
Force LTR Override
Disabled / Enabled
LTR Lock
Disabled / Enabled
Extra Options
NOTE
PCI Express Configuration
The BIOS entries and options on ports 1-3, 9 and 21 are identical. Port 1 is shown as an example