Commissioning
EL3773
137
Version: 2.5
the frames are not arriving regularly at the EL3773. In this case the above points should be checked.
• In particular the synchronization can become more difficult if such effects occur during the start-up
phase. This may also prevent the EL3773 from entering the OP state.
Fig. 153: Visualization of example program for EL3773
In this example the input data of an EL3773 will be checked for validity and processed:
• Cycle time and oversampling freely configurable, presetting: 5 ms cycle time, 20-fold oversampling
• WC, State, EtherCAT Master DevState, WcState, FrmState and status of the channels are cyclically
checked
• The data from each cycle are placed in a FIFO buffer so that, for example, the evaluation can take
place at a higher level. The size of the FIFO buffer is freely configurable
• If all data are valid, the following calculations take place:
◦ RMS voltage for each channel
◦ RMS current for each channel
Summary of Contents for EL3773
Page 1: ...Documentation EL3773 Power Monitoring Oversampling Terminal 2 5 2018 03 13 Version Date...
Page 2: ......
Page 6: ...Table of contents EL3773 6 Version 2 5...
Page 39: ...Mounting and wiring EL3773 39 Version 2 5 Fig 29 Other installation positions...
Page 41: ...Mounting and wiring EL3773 41 Version 2 5 Fig 31 Block diagram...
Page 47: ...Commissioning EL3773 47 Version 2 5 Fig 38 Incorrect driver settings for the Ethernet port...
Page 147: ...Commissioning EL3773 147 Version 2 5 Fig 168 Confirming program start...
