Beckhoff EL47 Series Documentation Download

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Commissioning

EL47xx

139

Version: 2.7

64- vs. 32-bit representation

Some EtherCAT slaves can only handle 32 bit values for representing the DC time or handle it as a
process data. In order to prevent problems caused by overflow (every 4.2 seconds), we strongly
recommend using 64-bit times in the controller.

• 32-bit times supplied to the PLC must be complemented with the current High part

• In this case only the Low part (lower 32 bit) should be transferred to the hardware

This sample project

(https://infosys.beckhoff.com/content/1033/el47xx/Resources/zip/2469155979.zip) contains a function

block that cyclically adds the high part to a 32-bit DC time to make 64 bits.

5.6.4

Time-related cooperation with other terminals

The process data output of the DAC (digital/analog converter) in the EL47xx is triggered by an interrupt,
which is generated by the local clock in the terminal. All local clocks in the supporting EtherCAT slaves are
synchronized. This enables EtherCAT slaves (here: terminals) to sample measured values and output values
simultaneously (simultaneous interrupt generation),

independent of the distance between them

. This

simultaneity is within the distributed clock precision range of < 100 ns.

Sample:

Matching between two EL4732:

The EtherCAT master, e.g. Beckhoff TwinCAT, configures both EL4732 such that their SYNC1 signals occur
at the same time. Assumption: The EtherCAT bus cycle time is 500 µs. SYNC1 is therefore triggered every
500 µs in all EL4732. If both terminals operate with a corresponding oversampling factor (e.g. 20), the
SYNC0 pulse correlating to SYNC1 will occur simultaneously in all EL4732, in this example every 25 µs.

If the EL4732 use different oversampling factors, their SYNC0 pulses no longer occur simultaneously. The
higher-level SYNC1 pulse is retained.

If a value is entered under "Shift time (µs)" in the TwinCAT System Manager (DC tab, Advanced Settings) for
the SYNC0 pulse in an EL4732, the EL4732 manipulated in this way will start output sooner or later,
according to the set value.

Sample:

An EL3702 oversampling input terminal scans an analog signal on 1 channel with an oversampling factor of
n = 100 and a bus cycle time of 1 ms. The sample resolution is therefore 10 µs. This signal should be output
accordingly on a EL4732 with same settings. Sample output in the EL4732 should be delayed by an exactly
defined interval. Please note:

• The EL4732 belongs to the output slave group and therefore features the standard shift time in the

SYNC1 pulse (see Beckhoff System Manager --> EtherCAT device --> EtherCAT tab --> Advanced
Settings --> Distributed Clocks --> Shift Time).

• The EL3702 belongs to the input terminal group and therefore features a slightly earlier SYNC1 pulse.

This forward shift depends on several parameters. See “Distributed clock system description”. Setting
also under Beckhoff System Manager --> EtherCAT device --> EtherCAT tab --> Advanced Settings -->
Distributed Clocks --> Shift Time.
"Input Shift Time" settings affect

all

input terminals.

• In addition, the shift time for the affected EL4732 (and the EL3702) can be modified via the System

Manager ("DC" tab, "Advanced Settings", "SYNC0", "User Defined"). If an

additional

shift time of 5 µs

is entered manually for the SYNC0 pulse for this terminal, each output is delayed by 5 µs relative to all
other (globally set) output terminals.

Synchronization and provision of process data

The SYNC1 pulse is derived from the SYNC0 pulse. Please note that this may influence the timing
of the process data allocation for the EtherCAT frame, since this is controlled by the SYNC1 pulse.