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BL3300 SERIES MANUAL 01/28/2013
SECTION 5
THEORY OF OPERATION
5.4.2
The variable frequency 45 to 500 Hertz square-wave is generated on the Motherboard. A CMOS
phase locked loop (U5), and 8 bit counter (U6) and Voltage Controlled Oscillator (U7) are the basis for the
square-wave generator. The front panel frequency control sets a DC voltage which determines the frequency
of the VCO. The VCO generates a square-wave at a frequency between 45 and 500 Hertz. This square-wave
is used as a reference signal for the PLL. The frequency of the VCO is multiplied by a factor of 256 by the
PLL. The resultant is used as a clock signal for the 8 bit counter.
5.4.3
In order to produce data in the form of a sine-wave, a "Look-up" table is stored in a PROM on each
phase control card. The outputs of the 8 bit counter are tied to the address lines of each PROM. As the clock
runs, the data in the PROMS are clocked into the D/A convertors. This action produces a series of steps at
the output of the D/A convertor that approximate a sine-wave. Further filtering produces a clean sine-wave
at the frequency of the VCO. Phase displacement is determined by the PROM data.
5.4.4
The mother board also produces a triangle-wave signal that is common to the PWM modulators
contained on the phase control cards discussed later.
5.4.5
All inter-connection between circuits and controls are provided via the Motherboard. Four 22 pin card
edge connectors are present for the installation of 3 phase control cards and a GPIB interface card.
Distribution of all low voltage supplies is via the Motherboard.
5.5 OUTPUT INVERTER
5.5.1
The 3 output inverters (3 phase units) are based on a half bridge topology. A 600 volt, 100 amp,
IGBT module is connected between the +/-250 Vdc rails. The drive signal to the inverter is a "sine weighted"
Pulse Width Modulated (PWM), isolated rectangular pulse train. The output of the half bridge is a 20 Khz
pulse train that swings 500 volts peak-to-peak and has a varying duty cycle based on the modulating signal
(sine-wave generator). This output is filtered by a low pass network. The result is a sine-wave voltage that
is an amplified version of the sine-wave signal.
5.5.2
Pulse Width Modulation is performed by the individual phase control cards. The tri-wave signal
generated by the Motherboard is distributed to each phase control card. Components U7, U12, U13, and U14
form a modulator circuit that provides a dual polarity PWM signal that is applied to optically-coupled driver IC's
U17 and U18. These driver IC's provide boosted, isolated, drive for the upper and lower IGBT of the output
invertor. The two inputs to the modulator are the 20 Khz tri-wave and the locally generated sine-wave.
5.5.3
The driver IC's provide short circuit protection via an isolated fault output. This circuit detects the VCE
voltage of the upper and lower IGBT. If the output of the inverter is shorted the IGBT's collector to the emitter
voltage will increase and trigger the short circuit detection. The fault detect signal is used to set a latching lock
out that turns off the PWM drive signals. The latch logic is comprised of U9, U10, U12 on the Motherboard.
The latch must be reset by cycling power.
5.5.4
The output amplitude of each phase is also regulated by the phase control card. A sample of the
output voltages fed to an RMS to DC convertor (U4). The resultant DC voltage is compared to a reference
DC voltage set by the front panel voltage control or remote interface. This comparison is performed by U3a
and is integrated to provide an error signal to control the amplitude of the sine wave signal fed to the PWM
modulator. Compensation for load line (wire) drops performed by summing in a signal form the current
monitor. The more current drawn, the more correction is provided. This compensation is adjustable via the
front panel.
5.6 METERING
5.6.1
Metering is provided by DC signals taken from the phase control cards. These signals are derived
from the voltage and current monitoring circuits. These signals are attenuated and applied to the front panel
DVM's. The frequency display derives it's data from the VCO signal.
Summary of Contents for BL3300 Series
Page 9: ...3 BL3300 SERIES MANUAL 01 28 2013 ALL MANUAL ADDENDUMS WILL FOLLOW THIS PAGE ...
Page 15: ...9 BL3300 SERIES MANUAL 01 28 2013 SECTION 2 UNPACKING AND INSTALLATION ...
Page 17: ...11 BL3300 SERIES MANUAL 01 28 2013 FIGURE 2 2 ...
Page 20: ...14 BL3300 SERIES MANUAL 01 28 2013 ...
Page 33: ...3 PHASE POWER CHASSIS MECHNICAL OUTLINE ...
Page 34: ...BL3300 CONTROL CHASSIS MECHANICAL OUTLINE ...
Page 35: ...BL33XX SERIES SINGLE PHASE POWER CHASSIS OUTLINE DRAWING 19 0 TYP 17 TYP 7 0 MAX ...
Page 54: ...6 1 SECTION 6 PARTS LIST AND DRAWINGS f ...
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