60
Technical
Reference
|
Bit
1:
Request
to
Send
(RTS)
Bit
2:
Out
1
(OUT
1)
Bit
3:
Out
2
(OUT
2)
Bit
4:
Loop
Bit
5:
Must
be
0
Bit
6:
Must
be
0
Bit
7:
Must
be
0
6
2
7
Line
Status
Register
(LSR)
Bit
0:
Data
Ready
(DR)
Bit
1:
Overrun
Error
(OR)
Bit
2:
Parity
Error
(PE)
Bit
3:
Framing
Error
(FE)
Bit
4:
Break
Interrupt
(BI)
Bit
5:
Transmitter
Holding
Register
Empty
(THRE)
Bit
6:
Transmitter
Shift
Register
Empty
(TSRE)
Bit
7:
Must
be
0
6
2
8
MODEM
Status
Register
(MSR)
Bit
0:
Delta
Clear
to
Send
(DCTS)
Bit
1:
Delta
Data
Set
Ready
(DDSR)
Bit
2:
Training
Edge
Ring
Indicator
(TERI)
Bit
3:
Delta
Receive
Line
Signal
Detect
(DSLSD)
Bit
4:
Clear
to
Send
(CTS)
Bit
5:
Data
Set
Ready
(DSR)
Bit
6:
Ring
Indicator
(RI)
Bit
7:
Received
Line
Signal
Detect
(RSLD)
6
2
9
Divisor
Latch
(LS,
MS)
LS
MS
Bit
0:
Bit
0
Bit
8
Bit
1:
Bit
1
Bit
9
