Central Switching Module PTN-CSM310-A/PTN-CSM540-A 17
Release 03 05/2020
b.
(=Precision Time Protocol)
The Precision Time PTP IEEE 1588v2 Protocol (=PTP), as defined in IEEE 1588v2, is a protocol
that manages the distribution of a synchronous timestamp clock (micro-second accuracy),
network wide between an external grandmaster clock and its slaves or substations. The CSM
verifies that all the IFMs in the node have the same node-internal timestamp. If not, the CSM
will raise an alarm. This node-internal timestamp must be the same on each IFM to guarantee
that the calculated node-traverse time needed for IEEE 1588 messages, will be consistent and
correct through the entire node. More detailed info can be found in Ref. [2Net] in Table 2.
PTP IEEE 1588v2 support: Verify the
‘
PROTOCOL AND FEATURE SUPPORT MATRIX
’ in the
HiProvision manual (Ref. [2Net] in Table 2) to find out which IFMs support this feature;
NOTE:
The figure below is an example with the CSM310-A. It is similar for the CSM540-A.
Figure 6
IEEE 1588v2
2.2.6
Layer2: Link Aggregation/LAG (=Link Aggregation Group) on CSM310-A
Link Aggregation is the bundling (=aggregation) of multiple physical Ethernet links between a
source and destination side into one combined logical Ethernet link. A LAG is a combination
of multiple Ethernet LAN ports within one logical port group, maximum 8 ports per LAG and 8
LAGs per node. The Link Aggregation is the communication between two LAGs. E.g. one LAG
in one Dragon PTN node and the second LAG in a third party switch/application. For 1G ports,
all the ports of the source and destination LAG must be in autonegotiation. On the Dragon
PTN side, ports with the same speed and linked to the same switch ASIC (CSM, L2 or L3) can
be added to the same LAG. Each bullet shows the possible LAG ports per switch ASIC:
CSM: all Ethernet IFM ports (4-GC-
LW, …) of the same speed in the same node;
L2: all 6-GE-L IFM ports;
L3: all 9-L3A-L / 9-L3EA-L IFM ports of the same speed;
NOTE:
Example: Ports in different nodes can not be added to the same LAG because they
are linked to different switch ASICs. CSM (4-GC-
LW, …), L2 and L3 ports in a same
node can not be added to the same LAG because they are linked to different switch
ASICs.
NOTE:
LAG on WAN ports and L2/L3 back end ports is not supported.
MPLS-TP
Dragon PTN
Grandmaster
Master
Slaves
Boundary Clock
Ordinary Clock
Ethernet Service: IEEE 1588v2
4-GC-LW
Ethernet
Ethernet
Ethernet
Transparent Clock
Transparent Clock