________________________________________________________________________________________________________________________________________________
The i.MX 6SoloLite processor incorporates the following hardware accelerato
•
GPU2Dv2—2D Graphics Processing Unit (BitBlt).
•
GPUVG—OpenVG 1.1 Graphics Processing Unit.
•
PXP—PiXel Processing Pipeline. Off loading key pixel processing operations are required to
support the EPD display applications.
Security functions are enabled and accelerated by the following hardware:
•
ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
•
SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features.
•
SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock.
•
CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level opera
well as the TZ policy.
•
A-HAB—Advanced High Assurance Boot
256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
Beta Touch Computer
____________________________________________________________________________________________________________________________________________
The i.MX 6SoloLite processor incorporates the following hardware accelerators:
2D Graphics Processing Unit (BitBlt).
OpenVG 1.1 Graphics Processing Unit.
PiXel Processing Pipeline. Off loading key pixel processing operations are required to
support the EPD display applications.
d and accelerated by the following hardware:
ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking
em debug features.
Volatile Storage, including Secure Real Time Clock.
Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
Advanced High Assurance Boot—HABv4 with the new embedded enhancements: SHA
bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
Beta Touch Computer
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PiXel Processing Pipeline. Off loading key pixel processing operations are required to
ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking
Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
tion mode as
HABv4 with the new embedded enhancements: SHA-
bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
