Bluetrum Technology AB53 Series, User Manual

Page 1: ...on Bluetrum reserves the right to make changes without further notice to any products herein to improve reliability function or design For further information on the technology product and business term please contact Bluetrum Company For sales or technical support please send email to the address Sales sales bluetrum com Technical project bluetrum com Bluetooth Speaker ARG SP 3016BK ...

Page 2: ...ory Date Version Comments Revised by 2018 07 03 0 0 1 First draft Leo 2018 07 12 0 0 2 Add PWM Hugo 2018 08 13 0 0 3 Add RTC Hugo 2018 08 24 0 0 5 Add QDID Hugo 2018 09 11 0 0 6 Update uart0baud description Leo 2018 09 27 0 0 7 Remove package Leo ...

Page 3: ... EXTERNAL PORT INTERRUPT WAKE UP 13 4 TIMER 15 4 1 FEATURES 15 4 2 TIMER0 1 2 SPECIAL FUNCTION REGISTERS 15 4 3 TIMER3 4 5 SPECIAL FUNCTION REGISTERS 16 5 PWM 18 5 1 FEATURES 18 5 2 SPECIAL FUNCTION REGISTERS 18 6 RTC 20 6 1 FEATURES 20 6 2 SPECIAL FUNCTION REGISTERS 20 6 3 INDEPENDENT POWER RTC REGISTERS 21 7 UART0 25 7 1 FEATURES 25 7 2 UART0 SPECIAL FUNCTION REGISTERS 25 7 3 USER GUIDE 26 8 SPI...

Page 4: ...Table of content 4 Copyright 2018 www bluetrum com All Rights Reserved 4 9 2 IO PARAMETERS 31 9 3 AUDIO DAC PARAMETERS 32 9 4 AUDIO ADC PARAMETERS 32 9 5 BT PARAMETERS 32 9 6 CURRENT PARAMETERS 33 ...

Page 5: ...w 1 1Introduce AB53XX is a 32 bits RISC microcontroller It integrates advanced digital and analog peripherals to audio player applications PMU Charger Buck CPU Memory Bluetooth ADC DAC PA SPDIF RX IIS FM RX FM TX SD MMC USB2 0 IR KEY SPI UART GPIO PWM LED PA CODEC Other Application DSP ENGINE ...

Page 6: ...AC and two channel 16bit ADC Support flexible audio EQ adjust Support Sample rate 8 11 025 12 16 22 05 32 44 1 and 48KHz 4 channel Stereo Analog MUX Two channel MIC amplifier input High performance Stereo audio ADC with 90dB SNR High performance Stereo audio DAC with 95dB SNR with headphone amplifier output Peripheral and Interfaces Three 32 bit timers Three multi function 32 bit timers support Ca...

Page 7: ...h priority interrupt see the following table High priority interrupt vectors Interrupt number Address Description 0 0x80 1 0x90 2 0xa0 Software interrupt 3 0xb0 Timer0 interrupt 4 0xc0 Timer1 interrupt 5 0xd0 Timer2 interrupt Timer4 interrupt Timer5 interrupt 6 0xe0 Timer3 interrupt IR receiver interrupt 7 0xf0 8 0x100 9 0x110 10 0x120 11 0x130 12 0x140 13 0x150 14 0x160 UART0 interrupt UART1 inte...

Page 8: ...ble Global interrupt enable mask 15 8 Unused 7 3 Unused 2 HPINTEN W 0 Write 1 enable High priority interrupt 1 LPINTEN W 0 Write 1 enable Low priority interrupt 0 GIE W 0 Write 1 enable Global interrupt Register 2 3PICCONCLR Peripheral interrupt control clear Register Bit Name Mode Default Description 31 17 Unused 16 GIEMDIS W 0 Write 1 disable Global interrupt enable mask 15 8 Unused 7 3 Unused 2...

Page 9: ... 1 high priority interrupt Register 2 8PICADR Peripheral interrupt address Register Bit Name Mode Default Description 31 10 BADR WR 0x40 Interrupt entry address 9 0 0x0 Register 2 9PICPND Peripheral interrupt pending Register Bit Name Mode Default Description 31 3 IntPND 31 4 R 0x0 Interrupt 31 to 4 pending bit 0 no interrupt pending 1 interrupt pending 2 SWIPND WR 0 Software interrupt pending Wri...

Page 10: ...scription 31 8 Unused 7 0 GPIOASET WO X Set Pax output data Write 1 set output data Write 0 affect nothing Register 3 3GPIOACLR Port A clear output data Register Bit Name Mode Default Description 31 8 Unused 7 0 GPIOACLR WO X Clear Pax output data Write 1 clear output data Write 0 affect nothing Register 3 4GPIOADIR Port A direction Register Bit Name Mode Default Description 31 8 Unused 7 0 GPIOAD...

Page 11: ...Default Description 31 8 Unused 7 0 GPIOAPD WR 0x0 PAx 300Ω pull down resister control Valid when PAx is used as input 0 disable 1 enable Register 3 11GPIOADE Port A digital function enable register Bit Name Mode Default Description 31 8 Unused 7 0 GPIOADE WR 0xFF PAx digital function enable 0 Port used as analog IO 1 Port used as digital IO Register 3 12GPIOAFEN Port A function mapping enable reg...

Page 12: ... these bits Others is reserved 11 8 UT0TXMAP WR 0x0 UART0 TX mapping 0000 no affect 0001 map to G1 0010 map to G2 0011 map to G3 0100 map to G4 0101 map to G5 0110 map to G6 0111 map to G7 1111 Clear these bits Others is reserved 7 4 SPI0MAP WR 0x0 SPI0 mapping 0000 no affect 0001 map to G1 0010 map to G2 0011 map to G3 1111 Clear these bits Others is reserved 3 0 SD0MAP WR 0x0 SD0 mapping 0000 no...

Page 13: ...ers is reserved 15 12 TMR4MAP WR 0x0 Timer4 PWM mapping 0000 no affect 0001 map to G1 1111 Clear these bits Others is reserved 11 8 TMR3MAP WR 0x0 Timer3 PWM mapping 0000 no affect 0001 map to G1 1111 Clear these bits Others is reserved 7 4 TMR3CPTMAP WR 0x0 Timer3 capture Pin mapping 0000 no affect 0001 map to G1 0010 map to G2 0011 map to G3 0100 map to G4 0101 map to G5 0110 map to G6 0111 map ...

Page 14: ...ng 1 wake up pending 15 8 Unused 7 0 WKEDG WR 0x0 Wake up input 7 0 wakeup edge select 0 rising edge 1 falling edge Register 3 19WKUPCPND Wake up clear pending Register Bit Name Mode Default Description 31 8 Unused 23 16 WKCPND W 0x0 Wake up input 7 0 clear pending 0 no affect 1 clear wake up pending 15 0 Unused Register 3 20PORTINTEN Port interrupt enable Register Bit Name Mode Default Descriptio...

Page 15: ...0x0 Increase clock selection 00 System Clock 01 Counter input rising 10 Counter input falling 11 Counter input edge 1 Unused 0 TMREN WR 0 Timer Enable Bit 0 Disable 1 Enable Register 4 2TMR0CPND TMR1CPND TMR2CPND Timer0 1 2 clear pending Register Bit Name Mode Default Description 31 16 Unused 9 TPCLR W 0 Timer overflow pending clear bit 0 inactive 1 clear pending 8 0 Unused Register 4 3TMR0CNT TMR...

Page 16: ...rupt enable 0 disable 1 enable 6 INCSRC WR 0 Increase source select 0 select TMR_INC 1 select external PIN 5 4 CPTEDSEL WR 0x0 Timer Capture edge select 00 No Capture 01 Capture PIN rising edge 10 Capture PIN falling edge 11 Capture PIN edge 3 2 INCSEL WR 0x0 Increase clock selection 00 System Clock 01 Counter input rising 10 Counter input falling 11 Counter input edge 1 CPTEN WR 0 Timer capture E...

Page 17: ...1 0 TMRCPT R x Timer capture value Register 4 10TMR3DUTY0 TMR4DUTY0 TMR5DUTY0 Timer3 4 5 pwm0 duty Register Bit Name Mode Default Description 31 16 Unused 15 0 TMRDUTY0 W x Timer pwm0 duty PWM0 low level length is TMRDUTY0 1 PWM 0 high level length is TMRPR TMRDUTY0 1 Register 4 11TMR3DUTY1 TMR4DUTY1 TMR5DUTY1 Timer3 4 5 pwm1 duty Register Bit Name Mode Default Description 31 16 Unused 15 0 TMRDUT...

Page 18: ...PWM01DUT PWM0 1 duty registers Bit Name Mode Default Description 31 16 PWM1DUT WR 0x0 PWM1 duty register Duty PWM1DUT PWMPR 15 0 PWM0DUT WR 0x0 PWM0 duty register Duty PWM0DUT PWMPR Register 5 4 PWM23DUT PWM2 3 duty registers Bit Name Mode Default Description 31 16 PWM3DUT WR 0x0 PWM3 duty register Duty PWM3DUT PWMPR 15 0 PWM2DUT WR 0x0 PWM2 duty register Duty PWM2DUT PWMPR Register 5 5 PWMCYCNUM ...

Page 19: ...efault Description PWM0STEP PWMPR Register 5 6 PWMSTEP PWM Step register Bit Name Mode Default Description 31 24 PWM3STEP WR 0x0 PWM3 Duty adjust step 23 16 PWM2STEP WR 0x0 PWM2 Duty adjust step 15 8 PWM1STEP WR 0x0 PWM1 Duty adjust step 7 0 PWM0STEP WR 0x0 PWM0 Duty adjust step ...

Page 20: ...ding 17 ALMPND R 0 RTC alarm pending 0 no pending 1 alarm pending 16 RTCPND R 0 RTC trans done 0 done 1 not done 15 9 Unused 8 ALM_WKEN WR 0 RTC alarm wakeup enable 0 disable 1 enable 7 RTC1S_WKEN WR 0 RTC 1S wakeup enable 0 disable 1 enable 6 VUSBRSTEN WR 0 VUSB insert reset system enable 0 disable 1 enable 5 WKUPRSTEN WR 0 RTC wake up power down mode reset system enable 0 disable 1 enable 4 ALMI...

Page 21: ...rm Register Bit Name Mode Default Description 31 0 RTCALM WR 0xffffffff 32bit RTC alarm Register 6 6 RTCCON0 RTC control Register 0 Bit Name Mode Default Description 7 PWRUP1ST WR 1 RTC first power up flag 0 not first power up 1 first power up 6 EXT32KS WR 0 External 32K select 0 use RTC internal 32K osc 1 use external 32K osc 5 RSV WR 1 Reserve can t be changed default value 4 RSV WR 0 Reserve ca...

Page 22: ...value 1 0 RSV WR 0x2 Reserve can t be changed default value Register 6 9 RTCCON3 RTC control Register 3 Bit Name Mode Default Description 7 RTC1S_WKEN WR 0 RTC one second wakeup enable bit 0 disable 1 enable 6 ALM_WKEN WR 0 RTC alarm wakeup enable bit 0 disable 1 enable 5 VSUB_WKEN WR 0 VUSB wake up enable bit 0 disable 1 enable 4 WKP_WKEN WR 0 WK pin wake up enable bit 0 disable 1 enable 3 Unused...

Page 23: ...trol Register 8 Bit Name Mode Default Description 7 5 Unused 4 VSUBP R 0 VUSB wake up pending 0 no pending 1 pending 3 WKP R 0 WK pin wake up pending 0 no pending 1 pending 2 RTC1SPC WR 0 When write RTC 1 second pending clear 0 no affect 1 clear 1s pending When read RTC 1 second pending 0 no second pending 1 second pending 1 ALMPC WR 0 When write RTC alarm pending clear 0 no affect 1 clear alarm p...

Page 24: ...6RTC 24 Copyright 2018 www bluetrum com All Rights Reserved 24 Bit Name Mode Default Description 0xa disable Others enable After enable can t disable ...

Page 25: ...X RX separate 1 TX RX one line 5 CLKSRC WR 0 Clock source select 0 system clock 1 uart_inc 4 SB2EN WR 0 Two Stop Bit enable 0 1 bit Stop Bit 1 2 bit Stop Bit 3 TXIE WR 0 Transmit Interrupt Enable 0 Transmit interrupt disable 1 Transmit interrupt enable 2 RXIE WR 0 Receive Interrupt Enable 0 Receiver interrupt disable 1 Receiver interrupt enable 1 BIT9EN WR 0 BIT9 Enable Bit 0 Eight bit mode 1 Nine...

Page 26: ... 1 15 0 UART0TXBAUD W 0 UART TX Baud Rate Baud Rate Fsys clock UART0TXBAUD 1 Register 7 4 UART0DATA UART Data Register Bit Name Mode Default Description 31 9 Unused 8 UART0BIT8 WR x UART Data bit 8 7 0 UART0DAT WR x UART Data Write this register will load the data to transmitter buffer Read this register will read the data from the receiver buffer 7 3User Guide 1 Set IO in the correct direction 2 ...

Page 27: ...x 1 finish SPI rx tx 15 11 Unused 10 SPIOSS WR 0 SPI output data and sample data is at the same edge 0 disable 1 enable 9 SPIMBEN WR 0 SPI multiple bit bus enable bit 0 disable 1 enable 8 SPILF_EN WR 0 SPI LFSR enable bit 0 disable 1 enable 7 SPIIE WR 0 SPI interrupt enable 0 disable 1 enable 6 SMPS WR 0 SPI sampling edge select bit when SPIOSS 0 output data and sample data is at different clock e...

Page 28: ...2bit bidirectional data bus 11 reserved 1 SPISM WR 0 Slave mode select bit 0 master mode 1 slave mode 0 SPIEN WR 0 SPI Enable Bit 0 Disable 1 Enable Register 8 2SPI1BAUD SPI Baud Rate Register Bit Name Mode Default Description 31 16 Unused 15 0 SPI1BAUD W 0 SPI Baud Rate Baud Rate Fsys clock SPI_BAUD 1 Register 8 3SPI1CPND SPI clear pending Register Bit Name Mode Default Description 31 17 Unused 1...

Page 29: ...unter Register Bit Name Mode Default Description 31 16 Unused 15 0 SPI1DMACNT W x SPIDMA byte counter Write this register will kick start spi send receive data Total number of bytes received send is SPI1DMACNT Register 8 6 SPI1DMAADR SPI1 DMA address Register Bit Name Mode Default Description 31 21 Unused 20 0 SPI1DMAADR W x SPIDMA byte address 8 3 User Guide SPI Normal 1bit Mode Operation Flow 1 ...

Page 30: ...process 8 If data bus width are 2 bit write SPIBUF twice kick start the transmission 9 However when receive data only need write once to kick start receive process 10 Wait for SPIPND to change to 1 or wait for interrupt 11 Read received data from SPIBUF if needed 12 Go to Step 8 to start another process if needed or turn off SPI by clearing SPIIE and SPIEN SPI1 DMA Mode Operation Flow 1 Set IO in ...

Page 31: ...3 0v ISC Short Circuit Current Limit 200 mA VBAT 3 8v Table 9 4 1 2V LDO Parameters Sym Characteristics Min Typ Max Unit Conditions VDDCORE 1 2V LDO voltage output 1 2 V Light Loading condition VVDDCORE Output Mismatch 1 sigma 20 mV VDDCORE 1 2v ILOAD Maximum output current 80 mA VBAT 3 6v ISC Short Circuit Current Limit 120 mA VBAT 3 8v 9 2 IO Parameters Table 9 5 I O Parameters GPIO Electrical C...

Page 32: ...ers Sym Characteristics Min Typ Max Unit Conditions SNR 90 dB VCM cap 1uF VDDDAC cap 1uF with A wt filter Input sine amplitude 850mV RMS Fin 1KHz THD N 87 dB VCM cap 1uF VDDDAC cap 1uF with A wt filter Input sine amplitude 850mV RMS Fin 1KHz Input Range Input sine wave peak amplitude 0 VCM V From aux input aux 0db gain VCM represent VCM voltage 9 5BT Parameters Table 9 8 BT Parameters Characterist...

Page 33: ...armful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or televi...