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4.4 Chipset Features Setup
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds
and the access to the system memory resources, such as DRAM and
the external cache. It also coordinates the communications between
the conventional ISA and PCI buses. It must be stated that these
items should never be altered. The default settings have been chosen
because they provide the best operating conditions for your system.
You might consider and make any changes only if you discover that
the data has been lost while using your system.
ROM PCI/ISA BIOS (2A59GD3G)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration
: Enabled
Delayed Transaction
:
Disabled
:
DRAM RAS# Precharge Time
: 3
DRAM R/W Leadoff Timing
: 7
Fast RAS To CAS Delay
: 3
DRAM Read Burst (EDO/FP)
: x444/x444
DRAM Write Burst Timing
: x444
Fast MA to RAS# Delay CLK
: 2
Fast EDO Path Select
: Disabled
Refresh RAS# Assertion
: 4 Clks
ISA Bus Clock
: PCI CLK/4
SDRAM (CAS Lat/RAS-to-CAS)
: 3/3
System BIOS Cacheable
: Disabled
Video BIOS Cacheable
: Disabled
8 Bit I/O Recovery Time
: 1
16 Bit I/O Recovery Time
: 1
ESC
: Quit
????
: Select Item
Memory Hole At 15M-16M
: Disabled
F1
: Help
PU/PD/+/-: Modify
Peer Concurrency
: Disabled
F5
: Old Values
(Shift) F2 : Color
Passive Release
Disabled
F6
: Load BIOS Defaults
F7
: Load Setup Defaults
