15
2.9 System Memory DRAM
The HS-6036 provides a wide SDRAM memory support with four
DIMM sockets request the access time should meet PC-133
standard (if use 133MHz FSB). The maximum capacity of the on
board memory is 1GB. Use memory module of the same brand and
size to avoid instability due to different access time.
2.10 Watchdog Timer
There are three access cycles of Watchdog Timer which are
Enable, Refresh and Disable. The Enable cycle should proceed by
READ PORT 443H. The Disable cycle should proceed by READ
PORT 045H. A continue Enable cycle after a first Enable cycle
means Refresh.
Once if the Enable cycle activity, a Refresh cycle is request before
the time-out period for restart counting the Watch-Dog Timer period.
Otherwise, it will assume that the program operation is abnormal
when the time counting over the period preset of Watchdog Timer. A
System Reset signal to start again or a NMI cycle to the CPU comes
if over.
The JP9 is using for select the active function of Watchdog Timer in
disable the Watchdog Timer, or presetting the Watchdog Timer
activity at the reset trigger, or presetting the Watchdog Timer activity
at the NMI trigger.
JP9 : Watchdog Active Type Setting
JP9 DESCRIPTION
1-2 Active
NMI
*2-3
System Reset
OFF
Disable Watch-Dog Timer
The Watchdog Timer is disabled after the system Power-On. The
Watchdog Timer can be enabled by a Enable cycle with reading the
control port (443H), a Refresh cycle with reading the control port
(443H) and a Disable cycle by reading the Watchdog Timer disable
control port (045H). After a Enable cycle of Watchdog Timer, user
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