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4.6 Advanced Chipset Features
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
the access to the system memory resources, such as DRAM and the
external cache. It also coordinates the communications between the
conventional ISA and PCI buses. It must be stated that these items
should never be altered. The default settings have been chosen
because they provide the best operating conditions for your system.
You might consider and make any changes only if you discover that the
data has been lost while using your system.
CMOS Setup Utility
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Copyright ©1984-2001 Award Software
Advanced Chipset Features
DRAM Clock
Host Clock
Item Help
DRAM Timing by SPD
Enabled
Menu Level
X
SDRAM Cycle Length
3
Bank Interleave
Disabled
Memory Hole at 15M-16M
Disabled
Change the day, month,
P2C/C2P Concurrency
Enabled
year and century
Fast R-W Turn Around
Enabled
System BIOS Cacheable
Enabled
Video BIOS Cacheable
Enabled
Video RAM Cacheable
Enabled
Frame Buffer Size
8M
AGP Aperture Size
64M
On Chip USB
Enabled
USB Keyboard Support
Disabled
On Chip Sound
Auto
CPU to PCI Write Buffer
Enabled
PCI Dynamic Bursting
Enabled
PCI Master 0 WS Write
Enabled
PCI Delay Transaction
Enabled
PCI#2 Access#1 Retry
Disabled
AGP Master 1WS Write
Disabled
Memory Parity/ECC Check
Disabled
: Select Item + / - /PU/PD: Value F10: Save ESC: Quit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Summary of Contents for HS-6050
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