CHAPTER 3 THEORY OF OPERATION
3-8
1.3.7 SDRAM
A 256Mbit SDRAM (x 16bit) is used as the RAM.
DATA_S[0]
DATA_S[8]
ADR[13]
DATA_S[4]
ADR[10]
DATA_S[5]
ADR[7]
DATA_S[12]
ADR[3]
DATA_S[14]
ADR[12]
ADR[11]
ADR[14]
ADR[4]
DATA_S[7]
ADR[9]
DATA_S[2]
ADR[5]
DATA_S[3]
ADR[2]
DATA_S[13]
ADR[8]
DATA_S[1]
ADR[6]
DATA_S[9]
DATA_S[10]
DATA_S[15]
DATA_S[6]
DATA_S[11]
TP50
C58
C103
U2
K4S561632
256bit
CS
19
RAS
18
CAS
17
WE
16
LDQM
15
UDQM
39
CLK
38
CKE
37
BA0
20
BA1
21
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A10/AP
22
A11
35
A12
36
NC
40
VDD1
1
VDD14
14
VDD27
27
VDDQ3
3
VDDQ9
9
VDDQ43
43
VDDQ49
49
VSS28
28
VSS41
41
VSS54
54
VSSQ6
6
VSSQ12
12
VSSQ46
46
VSSQ52
52
DQ0
2
DQ1
4
DQ2
5
DQ3
7
DQ4
8
DQ5
10
DQ6
11
DQ7
13
DQ8
42
DQ9
44
DQ10
45
DQ11
47
DQ12
48
DQ13
50
DQ14
51
DQ15
53
1-6A/3-1E/3-3C/3-4D/1E/6B/1A/3-1D
ADR[23-1]
C33
C103
C57
C103
1-6A/3-1D/3-1E/3-4D/1C/1E/6B
ADR[15]
BA0
1-6A/3-1E/3-3C/3-4D/1C/1E/6B
ADR[18]
CASN
0V
C61
C103
VDD3
1-6A/3-1E/3-3C/3-4D/1C/1E/6B
ADR[21]
DQM1
1-6A/3-1E/3-3C/3-4D/1C/1E/6B
ADR[19]
WEN
1-5C
SDCSN0
1-5C
SDCKE0
C60
C103
C59
C103
1-6A/3-1D/3-1E/3-4D/1C/1E/6B
ADR[16]
BA1
1-6A/3-1E/3-3C/3-4D/1C/1E/6B
ADR[20]
DQM0
1-6A/3-1E/3-3C/3-4D/1C/1E/6B
ADR[17]
RASN
1-5C
SDCLK0
C31
C103
3-6C/7C/6-1C
DATA_S[15-0]
SDRAM
Fig. 3-9