Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V1724 8 Channel 14bit - 100MS/s Digitizer
06/11/2007
7
NPO:
Filename:
Number of pages:
Page:
00103/05:V1724x.MUTx/07 V1724_REV7.DOC
63
13
2.4.4.
Digital I/O connectors
Function:
N.16 programmable differential LVDS I/O signals, Zdiff_in= 110 Ohm. Four
Indipendent signal group 0
÷
3, 4
÷
7, 8
÷
11, 12
÷
15, In / Out direction control; see also § 3.6.
Mechanical specifications:
3M-7634-5002- 34 pin Header Connector
2.4.5.
Optical LINK connector
Mechanical specifications:
LC type connector; to be used with Multimode 62.5/125µm cable with LC connectors on
both sides; not featured on Mod. V1724LC
Electrical specifications:
Optical link for data readout and slow control with transfer rate up to 80MB/s; daisy
chainable.
2.5.
Other front panel components
2.5.1. Displays
The front panel hosts the following LEDs:
Table 2.2 : Front panel LEDs
Name:
Colour:
Function:
DTACK
green
VME read/write access to the board
CLK_IN
green
External clock enabled.
NIM
green
Standard selection for CLK I/O (V1724LC Rev.0), TRG OUT, TRG IN, S IN.
TTL
green
Standard selection for CLK I/O (V1724LC Rev.0), TRG OUT, TRG IN, S IN.
LINK
green/yellow Network present; Data transfer activity
PLL _LOCK
green
The PLL is locked to the reference clock
PLL _BYPS
green
The reference clock drives directly ADC clocks; the PLL circuit is switched
off and the PLL_LOCK LED is turned off.
RUN
green
RUN bit set (see § 4.19)
TRG
green Trigger
accepted
DRDY
green
Event/data (depending on acquisition mode) are present in the Output Buffer
BUSY
red
All the buffers are full
OUT_LVDS
green
Signal group OUT direction enabled.
2.6. Internal
components
SW2..5 “Base Address [31:16]”: Type:
4 rotary switches
Function:
Set the VME base address of the module.
SW1 “CLOCK SOURCE”
Type Dip Switch
Function: Select clock source (External or Internal)
JP2 “FW”
Type:
Jumper.
Function: it allows to select whether the “Standard” or
the “Back up” firmware must be loaded at power on;
(default position: STD).
