INSTRUCTIONAL MANUAL
2750L-P/4500L-P/6000L-P
August, 2001
Rev. K
-30-
not installed. 5.0 VRMS on this pin will generate a full-scale output voltage.
J7-25
CL C: A DC level from the oscillator used to set the current limit for phase C. Make no connection to
this pin.
J7-26
CL A: A DC level from the oscillator used to set the current limit for phase A. Make no connection to
this pin.
J7-27
D COM: Digital common.
J7-28
RNG HI
: A logic output from the internal oscillator to control the range relays. A logic low on this pin indi-
cates the high voltage range. If the power system is used without an oscillator, this pin is a logic input.
J7-29
Make
no
connection.
J7-30
FLT B: Make no connection.
J7-31
F STB HI: Function Sync High signal. This is the collector lead of an optically isolated NON transistor.
The internal power controller turns this transistor on to indicate a change of programmed values. This
output will sink more than 2 milliamps to a TTL low logic output level (<.4 volts). The output is an
open, collector optocoupler output. A pullup resistor to a + VDC must be connected to J7, pin 31. J7,
pin 14, is the common output. Refer to Figure 3-3.
J7-32
EX SYNC HI: External Sync High signal. This is an input that can be used to synchronize the outputs
of the AC Power System. This input requires a logic high level of at least +4.5 VDC at 5 ma. The
input should have a duty cycle 50 ±30%. J7-15 is the common input. The External Sync input is
optically isolated. It must also be enabled from the SNC screen.
J7-36
REMOTE SHUTDOWN: This is a logic input that can be used to remove the programmed output
voltage. A logic low on this pin will cause the output voltages to be programmed to 0.0 volts and the
output relays to open. A logic high will cause the programmed output voltage to be restored at the
output terminals. A contact closure between this pin and J7-27 (D COM) will simulate a logic low state.
3.4.6
AUXILIARY OUTPUT (AX Option)
TB2 is the terminal block for the optional Auxiliary outputs. The Auxiliary outputs are fixed 26V rms, Phase D, and a 5V
rms, Phase E, output voltages. Refer to Figure 3-2 for the terminal identification for TB2.
J6 pins 5 and 6 are the External Sense input for the Phase D output. For the specified load regulation at the load, the
External Sense input should be connected across the Phase D load.
3.4.7 CLOCK
J1 is supplied on the master power source when the LK option is ordered. This signal is used by California Instruments
power controllers to synchronize oscillators in multiple power source systems. The connector is installed as an option.
3.4.8 LOCK
J2 is supplied on the master power source when the LK option is ordered. This signal is used by California Instruments
power controllers to synchronize oscillators in multiple power source systems. The connector is installed as an option.
3.4.9 DFI
(Discrete
Fault Interrupt)
J3 is supplied when the MT option is ordered. This BNC connector is wired to a relay in the power controller. The
Summary of Contents for 2750L-P Series
Page 119: ...INSTRUCTIONAL MANUAL 2750L P 4500L P 6000L P August 2001 Rev K 115 Figure 6 1 MODULE LOCATION...
Page 138: ...INSTRUCTIONAL MANUAL 2750L P 4500L P 6000L P August 2001 Rev K 134 Figure 14 EMERGENCY VOLTAGE...
Page 148: ...INSTRUCTIONAL MANUAL 2750L P 4500L P 6000L P August 2001 Rev K 144 FIGURE 2...
