COPYRIGHT © 2001 CANON INC. CANON CLC1000/1000S/3100 REV.2 MAY 2001 PRINTED IN JAPAN (IMPRIME AU JAPON)
A-15
APPENDIX
D. DC CONTROLLER CIRCUIT DIAGRAM
DC Controller Circuit Diagram (1/36)
D2220
+
Q2343
odd address
1
2
3
4
5
6
7
8
9
10
15
13
8
7
6
5
4
3
2
14
9
10
12
11
1
7
6
5
4
0
1
2
3
11
12
13
14
ML
WR*
RESET*
RAMCSO*
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/01
I/02
I/03
GND
VCC
xxx
A13
A8
A9
A11
CS2
A10
CS1*
I/08
I/07
I/06
I/05
I/04
+5V
+5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MRD*
C2366
R
OM1
Q2342
e
v
en address
1
2
3
4
5
6
7
8
9
10
15
13
8
7
6
5
4
3
2
14
9
10
12
11
1
10
12
13
15
0
9
10
11
11
12
13
14
MHWR*
RESET*
RAMCSO*
AB
US<23.,0>
DB
US<15.,0>
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/01
I/02
I/03
GND
VCC
xxx
A13
A8
A9
A11
CS2
A10
CS1*
I/08
I/07
I/06
I/05
I/04
+5V
+5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MRD*
C2353
R
OM2
Q2341
Q2340
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
B1
A1
96
95
94
93
92
91
90
89
88
87
B11
A11
B10
B9
B8
B7
B6
B5
B4
MLWR*
MHWR*
MRD*
B3
A3
A2
ECLK
CPUCLK
B34
A34
B33
A33
A31
B28
B27
86
85
MD2
MD1
MD0
VCC
RFSH*
LWR*
HWR*
RD*
AS*
E
O/
VSS
XT AL
EXT AL
VSS
P87/TXD2
P86/RXD2
P85/TXD1
P84/RXD1
P83/SCK2/IPG3*
P82/SCK1/IPG2*
P81/IPG1*
P80/IPG0*
VCC
AVCC
P73/AN3
P72/AN2
P71/AN1
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
46
47
48
49
50
51
52
53
54
55
56
A29
B29
A30
B30
B31
A32
B32
A33
B33
A34
B34
A35
B35
B36
A37
B37
A38
B38
A39
A1
B1
A2
B2
B3
A4
B4
B5
B6
A8
A9
A10
A11
A12
A13
A14
A15
VSS
A16/P20
A17/P21
A18/P22
A19/P23
A20/P24
A21/P25
A22/P26
A23/P27
VSS
WAIT*/P30
BACK*/P31
BREQ*/P32
P33
P34
P35
P36
P37
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
20
21
22
23
24
25
26
27
28
0
1
2
3
4
5
6
7
B12
RESET*
A13
B13
A14
B14
A15
A16
B16
A17
B17
B16
A19
B19
A20
A21
B21
A22
B22
A23
B23
A24
B24
A25
A26
B26
A27
B27
B28
STBY*
RES*
VSS
MMI
D0/P10
D1/P11
D2/P12
D3/P13
D4/P14
D5/P15
D6/P16
D7/P17
D8
D9
D10
D11
D12
D13
D14
D15
VSS
A0
A1
A2
A3
A4
A5
A6
A7
84
83
82
81
80
79
78
77
76
75
74
2
3
4
5
6
7
8
9
73
72
71
70
69
68
67
66
65
2
3
4
5
6
7
8
9
64
63
62
61
60
59
58
57
2
3
4
5
6
7
8
9
A
V55
V55
P67
P66
P65
P64
P63
P62
P61
P60
P57
P56
P55
P54
P53/FT
OB2
P52/FT
O
A
2
P51/FT
OB1
P50/FT
O
A
1
VSS
P47/FTCI2
P46/FTI2
P45/FTCI1
P44/FTI1
P43/TMO
P42/TMRI
P41/TMCI
ADTRG*/P40
B23
A21
B22
B21
A23
A22
B29
A30
A32
B31
A25
A26
B24
OhpSens
Hsync
PTXD
PRXD
HBAN3
REF 5V
HBAN2
B20
A20
B19
A19
B18
A18
A17
B16
Regi-Shutter
OHP-sense
Hopper-controll
F
an-controll
SoftSW
A16
B15
A15
B14
A14
A13
B12
A12
B11
A11
B10
B9
A9
B8
A8
A7
J2235
J2236
DB
US<15.,0>
24
15
R
OMCS0*
R
OMCS1*
+5V
+5V
+5V
+5V
+5V
+5V
CPUCLKA
RA2217
J2236
J2236
J2235
NC
+5V
+5V
Q2324
HB/510
HD641501BF
RA2221
RA2220
RA2219
RA2218
WDCK
HBAN1
HBAN0
J2236
B26
B25
J2236
J2236
C2320
C2322
C2343
C2321
80/68
CPU & R
OM & RAM
R2618
R2619
R2650
R2615
R2616
R2617
A28
A31
A36
B2
B15
B20
A5
A7
A12
B25
A4
A9
A8
A39
A40
B40
A6
A10
A18
J2235
J2235
+5V
+5V
+5V
A6
A5
A28
A27
J2236
J2236
J2236
X2202 21
9876
5
1
43
2
9876
5
1
43
2
+24R
+5V
+5V
R2417
R2415
R2418
R2340
R2416
Q2413
14
3
12
6
9
-
+
R2338
MainSW
1
2
1
2
1
2
1
2
1
2
1
2
CP2281
R2672
BA T2201
C2222
C2361
+
C2362
C2218
Q2456
C2273
Q2307
R2453
R2452
R2454
C2275
C2276
C2274
1
2
3
4
V
OUT
VSA
T
VIN
CT
CS*
RES*
GND
RES
8
7
6
5
1
2
3
4
Ct
RESET
Ck
GND
RESET*
Vs
Vret
VCC
8
7
6
5
WDCK
Q2306
9
10
8
RST*
HCD6
A3
A10
A24
A29
B13
B30
B17
B32
B7
P70/AN0
Summary of Contents for 1000S
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Page 840: ...0501GR PRINTED IN JAPAN IMPRIME AU JAPON This publication is printed on 100 reprocessed paper ...