— 41 —
Pin No.
Name
I / O
Function
1 ~ 12
KO1 ~ KO12
O
Key scanning signals
13 ~ 20
KI1 ~ KI8
I
Key scanning signals
27
TCH
I
Signal to CPU for the start of data transfer between PC and BN Unit
28
AVCC
I
Power supply to A/D converter of CPU
29
VREF
I
Reference voltage terminal for A/D converter
30
AVSS
Ground for A/D converter of CPU
37
BLD1
I
Signal to CPU for detection of low battery (2.1 V)
38
BLD2
I
Signal to CPU for detection of forced power off (1.6 V)
40, 41
BZ0, BZ1
O
Terminals for drive of buzzer
43
TXD
O
Terminal for serial data transfer (both PC LINK and MODEM)
44
RXD
I
Terminal for serial data transfer (both PC LINK and MODEM)
46
INT0
I
Interrupt signal from Gate array to CPU
48
NMI
I
Non maskable interrupt signal from Gate array (LSI2) to CPU
53
PORT8
O
Display ON/OFF signal from CPU to LCD driver LSI
54
PORT7
I
Signal to CPU for selection of BN Units (BN-10: no EL)
55
PORT6
I
Signal to CPU for control of external port for MODEM
56
PORT5
O
Signal to EL driver IC for control (power ON/OFF) of backlight
57
PORT4
O
Control signal for power supply to LCD (power ON/OFF)
58
PORT3
I
Wait signal from Gate array (LSI2)
59
PORT2
O
RESET signal to flash ROM (LSI304 and LSI306)
60
PORT1
I
Ready/Bussy signal from flash ROM (LSI304, 306, 308)
61
PORT0
O
RESET signal to Gate array (LSI2) and flash ROM (LSI308)
62
VSEL1
I
Power supply (5 V) to CPU
63
VSEL2
I
Power supply (3 V) to CPU
67
CS8B
O
not used
68
CS7B
O
Chip select signal to MASK ROM (LSI301) and LSI308
69
CS6B
O
Chip select signal to LSI for MODEM passing trough Gate array
70
CS5B
O
Chip select signal to flash ROM (LSI304)
71
CS4B
O
Chip select signal to flash ROM (LSI306)
72
CS3B
O
Control signal to data latch IC (IC151) for control of power supply to LCD
73
CS2B
O
Chip select signal to LSI (LSI4, 5) for LCD segment driver
74
CS1B
O
Chip select signal to Gate array (LSI302)
75
CS0B
O
Chip select signal to RAM (LSI303)
76
WEB
O
Write enable signal to LSI for memory and Gate array
77
OEBP
O
Clock (10MHz) to Gate array
78
OEB
O
Output enable signal to LSI for memory and Gate array
80
GND
Ground for CPU
81 ~ 103
A0 ~ A22
O
Address bus terminals
104
GND
Ground for CPU
105 ~ 120
D0 ~ D15
I/O
Data bus terminals
121
GND
Ground for CPU
129
SW
I
Signal from battery cover switch to CPU
130
GND
Ground for CPU
131
PO
O
Terminal for system clock (10.14 MHz)
132
PI
I
Terminal for system clock (10.14 MHz)
133
VCC1
I
Power supply to logic and oscillator circuit of CPU (2.2 V)
134
XO
O
Terminal for oscillator circuit of interior clock (32.768 kHz)
135
XI
I
Terminal for oscillator circuit of interior clock (32.768 kHz)
136
VCC2
I
Power supply to buzzer and keys
143
RESET
I
Reset terminal to CPU (from P key)
8. LSI PIN FUNCTION
8-1. CPU (LSI1)
This CPU is COB (Chip on board). Therefore this CPU cannot be replaced for repair.
CPU:UPD3066P (NC3020)
Summary of Contents for BN-10
Page 1: ...R BN 10 ZX 456 BN 20 ZX 457 NOV 1997 without price BN 20 ...
Page 49: ... 49 Main block PCB ASSY A140806 2 5 FM3416 Gate array ...
Page 51: ... 51 Main block PCB ASSY A140806 4 5 LINE DRIVER RECEIVER ...
Page 52: ... 52 Main block PCB ASSY A140806 5 5 AC Adapter Batteries ...
Page 55: ... 55 Display block LCD ASSY A140809 A140814 2 3 LCD common terminal driver ...
Page 56: ... 56 Display block LCD PCB ASSY A140809 A140814 3 3 LCD segment terminal driver ...
Page 57: ... 57 Cradle A140805 BN 10 20 PCB Z456 1 shielded ...