— 20 —
Pin No.
Pin Name
Input/Output
Function
1 ~ 14
KO14 ~ KO1
O
Key common signal
15 ~ 22
KI8 ~ KI1
I
Key input signal
23
BUFON
O
Chip select for RAM
24
IT2
I
Interrupt input
25
IT0
I
Interrupt input
26 ~ 46
AO20 ~ AO0
O
Address bus
47 ~ 54
IO0 ~ IO7
I / O
Data bus
55
OEBO
O
Output enable signal for RAM
56
WEBO
O
Write enable signal for RAM
64
CS3BO
O
Chip selecting signals
69 ~ 72
OPT3 ~ OPT0
O
Changeover signal
73
PORT7
I
Receiving terminal for data communication
74
PORT6
I
Receiving terminal for data communication
75
PORT5
O
Transmitting terminal for data communication
76
PORT4
O
Transmitting terminal for data communication
80
PORT0
I
Low battery message for back-up battery (2.6 V)
81
VSS
I
GND
82
PI
I
4.3 MHz clock input
83
PO
O
4.3 MHz clock output
84
VDD
I
+6 V source
85
XO
O
Clock output
86
XI
I
Clock input
87
VCC
I
+6 V source
88
VREG2
O
Voltage for main switch detection
89, 90
TS1, TS2
—
Test terminals of factory purpose only
91
VSSR
I
GND
94
VSS
I
GND
96
ITOFF
I
Switching terminal from main switch
97
TEMU
—
Test terminals of factory purpose only
98
SW
I
Receiving terminal for reset switch
99
VDB
I
+3 V source
100
VREG1
—
Test terminals of factory purpose only
101
VREG4
O
+3 V source for ROM
102
VREG5
—
Test terminals of factory purpose only
103
VDT1I
I
Forced power off detecting terminal (2.3 V)
104
VDT2I
I
Low battery message for main battery (2.5 V)
105
VREG3
—
+3 V source for RAM
CPU HCD62121A03 (HC-3017) : COB
NOTE: The CPU is bonding on the PCB. If the CPU is defective, replace the PCB ass'y because
the CPU cannot be replaced.
7. PIN FUNCTION
Summary of Contents for CFX-9850G PLUS
Page 1: ...R MAY 1997 CFX 9850G PLUS without price CFX 9850G PLUS ZX 935A ...
Page 25: ... 25 Main Block 1 11 SCHEMATIC DIAGRAMS ROM ...
Page 26: ... 26 Main Block 2 ...
Page 27: ... 27 Key Block To Main Block 1 ...
Page 30: ...23 25 24 22 20 19 21 18 17 4 6 7 LSI6 LSI5 30 13 EXPLODED VIEW 2 2 ...
Page 31: ...MA0500671A ...