— 76 —
error point:
Indicates the point on the memory where the operation instruction that causes the above general
exception is located (program counter).
However, an illegal address may be displayed depending on the exception code.
access adrs:
Indicates the address that is accessed according to the operation instruction that causes the above
general exception.
However, the address is 0 (zero) and has no meaning if the access is not the cause.
Error Code Correspondence Table
Causes of error occurrence
(1) error no. 40: TLB address comparison results in address mismatch
(2) error no. 60: TLB entry is invalid
Description of phenomenon:
The CPU performs a conversion from logical address to physical address when ac-
cessing the external memory.
TLB is what caches that information.
If an error occurs in the process of the caching, a general exception of the CPU oc-
curs.
Possible causes:
A malfunction of the CPU, because this is an internal operation of the CPU.
(3) error no. 80: Initial page write exception
Description of phenomenon:
This exception occurs if the address conversion table of the above TLB is illegally
written.
Possible causes:
A malfunction of the CPU, because this is an internal operation of the CPU.
(4) error no. A0: TLB protection exception (read)
(5) error no. C0: TLB protection exception (write)
Description of phenomenon:
TLB is protected by setting access right. An access that violates the access right
causes one of these exceptions to occur.
Possible causes:
A malfunction of the CPU, because this is an internal operation of the CPU.
(6) error no. E0: CPU address error (read)
(7) error no. 100: CPU address error (write)
Description of phenomenon:
This exception occurs if an illegal address is accessed (read or written).
Possible causes:
• An illegal address is accessed by software (a software bug).
• The address to be accessed has changed due to insufficient charge of the backup
battery for RAM.
error no.
error point
access adrs
Description of error
40
Location where error occurs Logical address of comparison source TLB address comparison results in address mismatch
60
Location where error occurs Logical address of error source
TLB entry is invalid
80
Location where error occurs Logical address of error source
Initial page write exception
A0
Location where error occurs Logical address of error source
TLB protection exception (read)
C0
Location where error occurs Logical address of error source
TLB protection exception (write)
E0
Location where error occurs Address of read destination
CPU address error (read)
100
Location where error occurs Address of write destination
CPU address error (write)
180
Location where error occurs 0
Reservation instruction code exception
1A0
Location where error occurs 0
Slot illegal instruction exception
Summary of Contents for QT-6100
Page 1: ...SERVICE MANUAL ELECTRONIC CASH REGISTER without price QT 6100 EX 819 AUG 2008 QT 6100 ...
Page 67: ... 65 8 11 ETHERNET CONTROLLER IC28 LAN91C113 8 11 1 Pin Assignment 8 11 2 Block Diagram ...
Page 92: ... 90 11 PCB LAYOUT MAIN PCB E819 1 PCB TOP VIEW ...
Page 93: ... 91 MAIN PCB E819 1 PCB BOTTOM VIEW ...
Page 94: ... 92 INTERFACE PCB E819 S1 PCB TOP VIEW BOTTOM VIEW LED PCB E820 LED PCB TOP VIEW BOTTOM VIEW ...
Page 108: ... 106 Model Name Board No Drawing No CASIO COMPUTER CO LTD QT 6100 EX 819 E820 LED LED ...
Page 120: ... 118 EXPLODED VIEW QT 6060D 2 11 17 14 15 20 Sales Option 16 5 6 12 13 18 19 8 7 10 3 1 4 9 5 ...
Page 135: ... 133 18 DRAWER DL 3616 ...
Page 137: ... 135 19 DRAWER DL 3617 ...
