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Bus State Controller (BSC):
Supports external extended memory access
• 16-bit (QFP-112, TQFP-120), or 32-bit (QFP-144) external data bus
Memory address space divided into five areas (four areas of SRAM space, one area of DRAM space) with the
following settable features:
• Bus size (8, 16, or 32 bits)
• Number of wait cycles
• Outputs chip-select signals for each area
• During DRAM space access:
Outputs RAS and CAS signals for DRAM
Can generate a RAS precharge time assurance Tp cycle
DRAM burst access function
• Supports high-speed access mode for DRAM
DRAM refresh function
• Programmable refresh interval
• Supports CAS-before-RAS refresh and self-refresh modes
Wait cycles can be inserted using an external WAIT signal
Address data multiplex I/O devices can be accessed
Direct Memory Access Controller (DMAC) (4 Channels):
Supports cycle-steal transfers
Supports dual address transfer mode
Can be switched between direct and indirect transfer modes (channel 3 only)
• Direct transfer mode: transfers the data at the transfer source address to the transfer destination address
• Indirect transfer mode: regards the data at the transfer source address as an address and transfers the data
at that address to the transfer destination address
Data Transfer Controller (DTC):
Data transfer independent of the CPU possible through peripheral I/O interrupt requests
Transfer mode can be set for each interrupt factor (transfer mode set in memory)
Multiple data transfers possible for one activating factor
Abundant transfer modes
• Normal mode/repeat mode/block transfer mode selectable
Transfer unit can be set to byte/word/longword
Interrupts activating the DTC requested of the CPU
• Interrupts can be generated to the CPU after completion of one data transfer
• Interrupts can be generated to the CPU after completing all designated data transfers
Transfer can be activated by software
