Celoxica RC200 Manual Download

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RC200/203 Manual

Contents

RC200/203

BOARD

.................................................................................................... 8

RC200/203

OVERVIEW

................................................................................................ 9

2.1

TANDARD KIT

...................................................................................................... 9

2.2

ROFESSIONAL KIT

............................................................................................. 10

2.3

XPERT KIT

........................................................................................................ 10

2.4

RC200/203

SUPPORT SOFTWARE

........................................................................ 11

NSTALLATION AND SET

........................................................................................ 12

ARDWARE DESCRIPTION

.......................................................................................... 13

4.1

RC200/203

DEVICES

.......................................................................................... 13

4.2

RC200/203

CONNECTORS

.................................................................................. 14

4.3

CPLD 14

4.3.1 Control and data pins ............................................................................................................ 14

4.3.2 CPLD clock............................................................................................................................ 15

4.3.3 Register map in the CPLD for the FPGA .............................................................................. 15

4.3.4 CPLD / parallel port interface ................................................................................................ 16

4.4

FPGA 18

4.4.1 FPGA operation modes......................................................................................................... 19

4.4.2 Programming the FPGA using the FTU2 program................................................................ 19

4.4.3 Programming the FPGA from the parallel port...................................................................... 19

4.4.4 Programming the FPGA from SmartMedia ........................................................................... 20

4.4.5 Programming from a specific address in the SmartMedia: ................................................... 20

4.4.6 Reading data from the CPLD to the FPGA ........................................................................... 20

4.4.7 Writing data to the CPLD from the FPGA ............................................................................. 21

4.4.8 Transferring data between the FPGA and host..................................................................... 21

4.4.9 Using the FPGA in parallel port control mode....................................................................... 21

4.5

ARALLEL PORT

................................................................................................. 21

4.6

MART

EDIA

LASH MEMORY

............................................................................. 22

4.6.1 SmartMedia connections to the CPLD .................................................................................. 22

4.6.2 FPGA access of SmartMedia ................................................................................................ 22

4.6.3 Parallel port access of SmartMedia ...................................................................................... 23

4.7

ZBT

SRAM

BANKS

............................................................................................ 23

4.8

LOCK GENERATOR

(PLL) .................................................................................. 24

4.8.1 Programming the PLL via the parallel port or FPGA............................................................. 25

4.9

THERNET

.......................................................................................................... 26

4.10

IDEO INPUT PROCESSOR

.................................................................................. 26

4.11

IDEO OUTPUT PROCESSORS

............................................................................. 27

4.11.1 Digital / Analogue converter ................................................................................................ 27

4.11.2 RGB to NTSC/PAL encoder ................................................................................................ 28

4.11.3 TFT flat panel display .......................................................................................................... 28

4.12

UDIO CODEC

................................................................................................... 28

4.13

RS-232

SERIAL TRANSMISSION

.......................................................................... 28

4.14

OUSE AND KEYBOARD

PS/2

PORTS

.................................................................. 29

4.15

SEGMENT DISPLAYS

....................................................................................... 29

4.16

ATA

XPANSION HEADER

................................................................................ 30

4.17

LED

.............................................................................................................. 32

4.18

ONTACT SWITCHES

......................................................................................... 32

4.19

ESET BUTTON

................................................................................................. 33

www.celoxica.com

Page 3

Summary of Contents for RC200

Page 1: ...Platform Developer s Kit RC200 203 Manual ...

Page 2: ...l warranties implied or express including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product Celoxica Limited shall not be liable for any loss or damage arising from the use of any information in this document or any incorrect use of the product The information contained herein i...

Page 3: ...ng data from the CPLD to the FPGA 20 4 4 7 Writing data to the CPLD from the FPGA 21 4 4 8 Transferring data between the FPGA and host 21 4 4 9 Using the FPGA in parallel port control mode 21 4 5 PARALLEL PORT 21 4 6 SMARTMEDIA FLASH MEMORY 22 4 6 1 SmartMedia connections to the CPLD 22 4 6 2 FPGA access of SmartMedia 22 4 6 3 Parallel port access of SmartMedia 23 4 7 ZBT SRAM BANKS 23 4 8 CLOCK G...

Page 4: ...e address mask 41 5 7 4 Reading from RAM 42 5 7 5 Writing data to RAM 42 5 8 PS 2 PORT MACROS 42 5 8 1 Mouse management tasks 42 5 8 2 Reading data from the mouse 42 5 8 3 Writing data to the mouse 43 5 8 4 Keyboard management tasks 43 5 8 5 Reading data from the keyboard 43 5 8 6 Writing data to the keyboard 43 5 9 RS 232 PORT MACROS 44 5 9 1 RS 232 management tasks 44 5 9 2 Reading from the RS 2...

Page 5: ...57 5 15 1 Using the SmartMedia macros 58 5 15 2 SmartMedia management tasks 59 5 15 3 Initializing the SmartMedia device 59 5 15 4 SmartMedia manufacturer and device code 59 5 15 5 Resetting the SmartMedia 60 5 15 6 Erasing SmartMedia memory 60 5 15 7 Number of pages per block 60 5 15 8 Logical and physical addressing 60 5 15 9 Reading from and writing to the SmartMedia 62 5 16 ETHERNET MACROS 64 ...

Page 6: ...d is th the numbe with 0x in comm at of prefixing r on with standard C syntax s me DestinationFileName struct rackets around an element show that it is optional but it may be repeated any number of times string character Sections of code or commands that you must type are given in typewriter font like this void main Information about a type of object you must specify is given in italics like thi c...

Page 7: ...Manual are familiar with common programming terms e g functions are familiar with your operating system Linux or MS Windows This manual does not include instruction in VHDL or Verilog instruction in the use of place and route tools tutorial example programs These are provided in the Handel C User Manual www celoxica com Page 7 ...

Page 8: ...nal part number RC I 200 2V1K4P Expert part number RC I 200 2V1K4E The RC203 is also available in 3 versions Standard part number RC I 203 2V3K4S Professional part number RC I 203 2V3K4P Expert part number RC I 203 2V3K4E Except where specifically noted in this document RC200 should be taken as meaning either RC200 or RC203 Note On the RC203 platform it is very important not to use any pins not sp...

Page 9: ...irtex II device on the RC203 has part number XC2V3000 FG676 2 1 Standard kit Virtex II 2V1000 4 RC200 or 2V3000 4 RC203 FPGA Ethernet MAC PHY with 10 100baseT socket 2 banks of ZBT SRAM providing a total of 4 MB Video support including Composite video in out S Video in out VGA out Camera in Camera socket provides camera power AC 97 compatible Audio including www celoxica com Page 9 ...

Page 10: ...lock pins JTAG connector Perspex top and bottom covers Universal 110 240V power supply IEC Mains lead not included Celoxica Platform Developer s Kit including Platform Support Library for RC200 203 Platform Abstraction Layer for RC200 203 Data Stream Manager for MicroBlaze soft core microprocessor FTU2 BIT file transfer utility for Windows NT4 Windows 2000 and Windows XP 2 2 Professional kit This ...

Page 11: ... Platform Developer s Kit RC200 Platform Support Library PSL RC200 Platform Abstraction Layer PAL implementation Data Stream Manager DSM implementation for MicroBlaze soft core microprocessor FTU2 program for Windows NT4 Windows 2000 and Windows XP Allows you you to download BIT files onto the FPGA www celoxica com Page 11 ...

Page 12: ...f connectors see page 14 You will need to connect the board to your PC with an IEEE 1284 compliant parallel port cable if you want to use the Celoxica FTU2 program to download BIT files or to read from or write to SmartMedia memory A cable is provided as part of the RC200 203 kit Switching on the power You need a 12V DC power supply with a 2 1mm centre positive plug The power supply must be able t...

Page 13: ...ation PSL RC200 RC200VBDOC pdf for the RC200 or in InstallDir PDK Documentation PSL RC203 RC203VBDOC pdf for the RC203 for installations using PDK3 1 or later Note On the RC203 platform it is very important not to use any pins not specifically referenced in this document To do so risks damaging the FPGA device There is also a list of data sheets see page 34 for the devices 4 1 RC200 203 devices DE...

Page 14: ...CPLD can configure the FPGA with data received from SmartMedia memory or via the parallel port 4 3 1 Control and data pins The RC200 CPLD has 10 control lines and 8 data lines 3 of the control lines are used as an address bus The control lines have two meanings depending on the FPGA operation mode see page 19 The FPGA operation mode is determined by whether the CPLD pin P9 is set high or low www c...

Page 15: ...t P8 V22 Y24 nCS Not Chip Select Output nDATA Output P9 T18 V20 Set high Set low CPLD data line RC200 FPGA pin RC203 FPGA pin FD0 V18 Y20 FD1 V17 VY19 FD2 W18 AA20 FD3 Y18 YAB20 FD4 Y5 AB7 FD5 W5 AA7 FD6 AB4 AD6 FD7 AA4 AC6 4 3 2 CPLD clock The RC200 CPLD has a clock input of 50MHz from a 50MHz crystal oscillator module This is divided by 2 to give an internal clock speed of 25MHz 4 3 3 Register m...

Page 16: ...3 SmartMedia nBUSY signal Bit 4 SmartMedia Detect 1 SmartMedia inserted Bit 5 SmartMedia not Write Protect Bit 6 SmartMedia state machine disable status Bit 7 PLL data line I2 C bus 2 Data bus access of the SmartMedia 3 Upper byte of Block address for the SmartMedia only the lower 5 bits are used 4 Lower byte of Block address for the SmartMedia 5 Read from this address to start reprogramming of th...

Page 17: ...ta lines the 8 values within the 3 bit CPLD address are used as follows Address value Description 0 Read and write i e data pins when FPGA is in parallel port control mode 1 Read and write from host for SmartMedia 2 Not used 3 Read status of signals 8 bit data line from CPLD Bit 0 Master FPGA DONE signal Bit 1 not used undefined Bit 2 FPGA nINIT signal Bit 3 SmartMedia nBUSY signal Bit 4 SmartMedi...

Page 18: ...x Virtex II FPGA part XC2V1000 4FG456C on RC200 and XC2V3000 4FG676 on RC203 The device has direct connections to the following devices CPLD ZBT RAM Ethernet Clock generator Video input Video DAC RGB to PAL NTSC encoder Audio codec RS 232 PS 2 connectors Expansion header 2 seven segment displays 2 blue LEDs 2 contact switches Bluetooth if fitted TFT Flat screen if fitted Touchscreen if fitted Deta...

Page 19: ...oard may not return the ID if the FPGA is controlling the parallel port If this happens eject the SmartMedia card and press the Reset button 2 Disable and clear the FPGA by asserting nPROG CPLD address 3 bit 4 Leave nPROG asserted 3 Disable the SmartMedia state machine by asserting CPLD address 3 bit 3 and leave this asserted during programming 4 Wait at least 1mS 5 Deassert nPROG 6 Wait for nINIT...

Page 20: ...equired CPLD reads the page valid byte 512 5 to see if it is valid If the page valid byte is invalid it searches though the block checking the page valid byte until it finds a page that is valid The first valid page is skipped if programming from address zero this is the CIS page Data is copied to the FPGA until the FPGA is DONE Bad pages are skipped The CPLD automatically adds 16 clock cycles aft...

Page 21: ... via the parallel port to the FPGA 1 Set nRDWR low 2 Set PnCS low 3 Send the data 4 Set PnCS high 5 Set nRDWR high To read data from the FPGA and write it to the host via the parallel port 1 Set nRDWR high 2 Set PnCS low 3 Read the data 4 Set PnCS high 5 Set nRDWR low 4 4 9 Using the FPGA in parallel port control mode When the CPLD control line P9 is set low the RC200 FPGA has direct control over ...

Page 22: ...blocks For more information on SmartMedia devices please refer to the RC200 Datasheets see page 34 The RC200 SmartMedia is connected to the CPLD on the following pins artMedia pins ls D pins 4 6 1 SmartMedia connections to the CPLD Sm Signa CPL 2 CLE 17 3 ALE 15 4 SMnWE 1 SMnCS 16 the FPGA via the CPLD A typica address 1 bit 4 A value of 1 successfully detected 13 5 nWP 11 6 SMD0 10 7 SMD1 9 8 SMD...

Page 23: ...he SmartMedia from th 1 Check the SmartMedia device is fitted address 3 bit 4 2 Disable the FPGA from accessing the SmartMedia by asserting nPRO 3 Disable the SmartMedi 4 Wait for at least 1mS 5 Assert nCS address 3 bit 0 6 Deassert ALE address 3 bit 2 7 Assert CLE address 3 bit 1 Write a SmartMedia command to CPLD address 2 For example refer to t www ssfdc or 9 Deassert CLE 4 7 ZBT SRAM banks The...

Page 24: ...0C4 S0C7 Not Byte Enable pins J20 K19 H20 J19 L22 M21 K22 L21 Pins connecting RAM Bank 1 to the FPGA SSRAM pin Function RC200 FPGA pins in ascending order RC203 FPGA pins in ascending order S1D0 S1D35 Data 35 0 D7 C7 D8 C8 D9 C9 D10 C10 E11 F11 E4 E5 E6 E7 E8 E9 E10 F9 F10 C2 C1 D2 D1 E2 F2 F1 G2 G1 H2 J2 J1 K2 K1 L2 E3 F4 F9 E9 F10 E10 F11 E11 F12 E12 G13 H13 G6 G7 G8 G9 G10 G11 G12 H11 H12 E4 E3...

Page 25: ...on a power on reset The PLL chip supports a form of I2 C If you are programming from the parallel port the FPGA should be disabled by asserting nPROG if there is any chance of it interfering with the programming of the PLL 2 If you program any of the clocks apart from CLKUSER you could stop the devices from working or damage them Programming the PLL from the parallel port Three bits in the CPLD ar...

Page 26: ...R22 R21 EC5 Not Read P20 T22 EC6 Not Write P19 T21 EC7 Interrupt R20 U22 EC8 Asynchronous ready pin Ardy R19 U21 EC9 Reset T20 V22 4 10 Video input processor The RC200 203 board is fitted with a Philips SAA7113H Video Input Processor enabling the FPGA to capture S Video CVBS and Camera input The FPGA can decode RGB to NTSC or PAL using the AD725 RGB to NTSC PAL encoder VGA output using the ADV7123...

Page 27: ... RC200 data sheets see page 34 DAC pins Function FPGA Pins in ascending order FPGA Pins in ascending order RGB0 RGB9 Red 9 0 U18 V16 V15 V14 V13 U14 U13 AB10 AA10 AB9 W20 Y18 Y17 Y16 Y15 W16 W15 AD12 AC12 AD11 RGB10 RGB19 Green 9 0 AA9 AA8 U11 V11 Y11 Y10 W10 AB18 AB15 Y9 AC11 AC10 W13 Y13 AB13 AB12 AA12 AD20 AD17 AB11 RGB20 RGB29 Blue 9 0 W9 Y8 W8 Y7 W7 Y6 W6 AB8 AB5 U10 AA11 AB10 AA10 AB9 AA9 AB...

Page 28: ... connected directly to the FPGA TFT control pins Function RC200 FPGA pins RC203 FPGA pins LCD0 Clock pin AA12 AC14 LCD1 Hsync pin W17 AA19 LCD2 Vsync pin Y17 AB19 LCD3 Data enable pin W16 AA18 The TFT has 18 data pins RGB4 RGB9 RGB14 RGB19 and RGB24 RGB29 These pins are shared by the TFT and the DAC on the FPGA 4 12 Audio codec The Cirrus Logic CS4202 is an AC 97 compliant stereo audio codec which...

Page 29: ...standard PS 2 mouse or keyboard The DATA and CLK lines of these sockets are mapped directly through to the FPGA The board supplies 5v to power the devices but they should not use more than 100mA PS 2 pins Description RC200 FPGA pins RC203 FPGA pins KM0 Mouse DATA P5 T7 KM1 Mouse CLK R5 U7 KM2 Keyboard DATA T5 V7 KM3 Keyboard CLK U5 W7 4 15 7 segment displays There are two 7 segment displays on the...

Page 30: ...FPGA pins A2 a J4 L6 B2 b J3 L5 C2 c H5 K7 D2 d F5 H7 E2 e L6 N8 F2 f H3 K5 G2 g G5 J7 DP2 decimal place K4 M6 4 16 ATA Expansion header The RC200 203 has a 50 pin expansion header including 34 general I O pins 3 power pins 12V 5V 3 3V and 2 clock pins You can also use 40 of the pins for ATA but only UDMA4 or higher devices are supported 2 The FPGA expansion header pins can only accept signals up ...

Page 31: ...IO12 P3 T5 14 D13 IO11 P4 T6 15 D1 IO14 R4 U6 16 D14 IO13 R3 U5 17 D0 IO16 T3 V5 18 D15 IO15 T2 V4 19 GND GND 20 Keypin Pin removed 21 DMARQ IO17 T1 V3 22 GND GND 23 nDIOW IO18 U1 W3 24 GND GND 25 nDIOR IO19 T4 V6 26 GND GND 27 IORDY IO20 U4 W6 28 CSEL IO21 V3 Y5 29 nDMACK IO22 V4 Y6 30 GND GND 31 INTRQ IO23 W1 AA3 32 Reserved IO24 W2 AA4 33 DA1 IO25 U2 W4 34 nPDIAG IO26 U3 W5 35 DA0 IO27 N6 R8 36...

Page 32: ...llows LED pins RC200 FPGA Pins RC203 FPGA Pins Blue0 J6 L8 Blue1 K6 M8 The LED pins should be set high to turn the LEDs on There are also two LEDs indicating when power is on for the board LED D2 and when the FPGA has been programmed LED D1 These are located to the left of the Celoxica copyright mark on the board They are controlled by the CPLD and you cannot program them from the FPGA 4 18 Contac...

Page 33: ...he chain is as follows The order of the devices in the JTAG chain is CPLD 0 FPGA 1 Video Decoder chip 2 The instruction register IR length for these devices is 5 5 3 respectively 4 21 Camera and camera socket The RC200 203 camera connector takes a standard Composite PAL or NTSC video signal 1v pp terminated into 75 Ohms A 3 pin connector is used so that power can be supplied to the camera 12v 50mA...

Page 34: ...42 6 4 inch touch screen is provided as an optional feature with the RC200 203 Expert board The touch screen controller is a Burr Brown Products TSC2200 It is connected directly to the FPGA For more details on these devices refer to the RC200 data sheets see page 34 Touch screen RC200 FPGA pins RC203 FPGA pins nPENIRQ Y14 AB16 nCSTOUCH W14 AA16 SPI CLK Y16 AB18 SPI DIN W15 AA17 SPI DOUT Y5 AB17 4 ...

Page 35: ...113H Video Input Processor http www semiconductors philips com pip SAA7113H_V1 html Analog Devices ADV7123 High Speed Video DAC http www analog com productSelection pdf ADV7123_b pdf Analog Devices AD725 RGB to NTSC PAL encoder http www analog com productSelection pdf 2302_0 pdf Optrex T 51382D064J FW P AA thin film transistor http www optrex com SiteImages PartList SPEC 51382AA pdf Cirrus Logic A...

Page 36: ...re the FPGA from SmartMedia and send data between the FPGA and host PC For information on the RC200 devices refer to the RC200 Hardware guide 5 1 Using the RC200 PSL Check that the DK library and include paths are set to InstallDir PDK Hardware Lib and InstallDir PDK Hardware Include You can set these in the Tools Options Directories dialog in DK Before you include the library in your source code ...

Page 37: ...K_RATE If RC200_TARGET_CLOCK_RATE is set to 24576000 25175000 or 50000000 then the 24 576MHz 25 175MHz or 50MHz on board clocks will be used respectively Otherwise a DCM will be used in frequency synthesis mode to generate the nearest approximation to the desired frequency from a base of 50MHz Note that the performance of generated clocks in terms of parameters like jitter may be worse than native...

Page 38: ... a specific LED To control both LEDs at once use RC200LEDWriteMask 5 4 1 RC200LEDWrite extern macro proc RC200LEDWrite Index Value Parameters Index LED index of type unsigned 1 Value Boolean control value of type unsigned 1 Timing 1 clock cycle Description Turns the Index number LED either on or off A Value of 1 means ON and 0 means OFF 5 4 2 RC200LED Write macros extern macro proc RC200LED0Write ...

Page 39: ...utton0Read extern macro expr RC200Button1Read Parameters None Return value Boolean button state of type unsigned 1 Description Reads a value from push button 0 or 1 5 5 3 RC200ButtonReadMask extern macro expr RC200ButtonReadMask Parameters None Return value Bitmask of button state of type unsigned 2 Description Reads a value from both of the push buttons The value at bit 0 is the state of button 0...

Page 40: ...200SevenSeg0WriteDigit Value DecimalPoint extern macro proc RC200SevenSeg1WriteDigit Value DecimalPoint Parameters Value Control value of type unsigned 4 DecimalPoint Control value of type unsigned 1 Timing 1 clock cycle Description Sets a particular hex digit 0123456789abcdef in the seven segment display Value is the hex value and DecimalPoint specifies whether the decimal point should be turned ...

Page 41: ...eAddress Address Parameters Address Address of data to read write on the next clock cycle of type unsigned 19 on the Standard and Professional versions of the RC200 and unsigned 20 on Expert boards Timing 1 clock cycle Description Sets the address of data for the Read or Write which will occur on the next cycle Example seq RC200PL1RAM0SetReadAddress Addr RC200PL1RAM0Read Data 5 7 3 Write address m...

Page 42: ...ingle item of data to the address specified by the call to RC200PL1RAM SetWriteAddress on the previous clock cycle 5 8 PS 2 port macros To write data to or read data from the mouse or keyboard you need to 1 Call RC200PS2MouseRun or RC200PS2KeyboardRun 2 Call the appropriate read macro or write macro in parallel with this 5 8 1 Mouse management tasks extern macro proc RC200PS2MouseRun ClockRate Par...

Page 43: ... you should use the PAL PS 2 API 5 8 4 Keyboard management tasks extern macro proc RC200PS2KeyboardRun ClockRate Parameters ClockRate Clock rate of the clock domain of the call to this macro in Hz Timing Does not terminate in normal use Description Runs the device management tasks for the keyboard You must run this macro in parallel with accesses to the device 5 8 5 Reading data from the keyboard ...

Page 44: ...32Run BaudRate Parity FlowControl ClockRate Parameters BaudRate A code selecting the initial baud Use the baud codes set by RC200RS232SetBaudRate Parity A code selecting the initial parity Use the parity codes set by RC200RS232SetParity FlowControl A code selecting the initial flow control Use the flow codes set by RC200RS232SetFlowControl ClockRate Clock rate of the clock domain of the call to th...

Page 45: ...ing the parity Possible values RC200RS232ParityNone RC200RS232ParityEven RC200RS232ParityOdd These correspond to the following settings no parity bit even parity bit odd parity bit Timing 1 clock cycle Description Changes the parity setting of the RS 232 interface Selecting the flow control extern macro proc RC200RS232SetFlowControl FlowControl Parameters FlowControl A code selecting the flow cont...

Page 46: ... Data 5 10 Touch screen macros You can use the touch screen macros to determine the position of the pointing device RC200TouchScreenReadRaw determines the position in raw coordinates RC200TouchScreenReadScaled determines the position scaled to 640 x 480 resolution You need to run these macros in parallel with RC200TouchScreenRun 5 10 1 Touch screen management tasks extern macro proc RC200TouchScre...

Page 47: ...to an lvalue of type unsigned 10 YPtr Pointer to an lvalue of type unsigned 9 TouchPtr Pointer to an lvalue of type unsigned 1 Timing 1 clock cycle Description Returns the last sensed position of the pointing device on the touch screen scaled to 640 x 480 resolution the same as the LCD screen underneath Note that the calibration of this scaling is only approximate for precision use each should be ...

Page 48: ...th displays Mode expression Video mode RC200VGAOutMode480at60 480 lines at 60Hz refresh RC200VGAOutMode480at75 480 lines at 75Hz refresh RC200VGAOutMode600at60 600 lines at 60Hz refresh RC200VGAOutMode600at72 600 lines at 72Hz refresh RC200VGAOutMode768at60 768 lines at 60Hz refresh RC200VGAOutMode768at76 768 lines at 76Hz refresh RC200VGAOutMode864at72 864 lines at 72Hz refresh RC200VGAOutMode102...

Page 49: ...00VideoOutGetTotalYCT Mode Ï Y resolutions are independent of clock rate Parameters in Hz Used to determine the horizontal screen Description to r of rows and tion parameter As a result the return value is also a compile time constant o proc RC200Vi Disable rs escription Disables the video output Mode A video mode expression ClockRate Clock rate of the clock domain of the call to RC200VideoOutRun ...

Page 50: ... or vertical sync status of the current unsigned 1 RC200VideoOutWrite24 RGB24 extern macro proc RC200VideoOutWrite30 RGB30 Parameters RGB24 Compound colour expression of type unsigned 24 RGB30 Compound colour expression of type unsigned 30 1 clock cycle Writes a single pixel to the display at the current scan position In both cases the video output expression is a co and blue components i e R G B ...

Page 51: ...s sample 5 12 3 Selecting the colour encoding standard extern macro proc RC200VideoInSetStandard Standard V deo input macros different macros for read RC200VideoInReadPixelPairYCrCb reads a pair of YCr native output from the video decoder and so this macro require other two read macros RC200VideoInReadPixelPairRGB RC200VideoInReadPixelRGB reads a single RGB pixel use one of these macros you need t...

Page 52: ...xels from the video input selected by RC200VideoInSetInput YCrCb is the native output from the video decoder and therefore requires the least hardware After the macro returns XPtr YPtr are the coordinates of the most recently sampled pixel which has the colour value YCrCbPtr Each pixel pair is presented at most once pixels can be missed if they are not read quickly enough at a rate of 6 75 MHz dur...

Page 53: ... line of 720 pixels The value returned in YPtr varies from 0 to the number of visible lines 1 0 575 for PAL and 0 479 for NTSC 5 12 6 Reading a single RGB pixel extern macro proc RC200VideoInReadPixelRGB XPtr YPtr RGBPtr Parameters XPtr Pointer to an lvalue of type unsigned 9 YPtr Pointer to an lvalue of type unsigned 9 RGBPtr Pointer to an lvalue of type unsigned 24 Timing 1 or more clock cycles ...

Page 54: ...odec You must run this macro in parallel with accesses to the device 5 13 2 Setting the audio input extern macro proc RC200AudioInSetInput Input Parameters Input Either RC200AudioInLineIn or RC200AudioInMicrophone Timing 1 or more clock cycles Description Sets the input of the audio ADC to be either the line in connector or the microphone 5 13 3 Boosting the input amplifier RC200AudioInSetMicropho...

Page 55: ...11025 11025 RC200AudioSampleRate16000 16000 RC200AudioSampleRate22050 22050 RC200AudioSampleRate32000 32000 RC200AudioSampleRate44100 44100 RC200AudioSampleRate48000 48000 default Timing 1 clock cycle Description Changes the sample rate of the audio input 5 13 6 Reading from the audio interface extern macro proc RC200AudioInRead LeftPtr RightPtr Parameters LeftPtr Pointer to an lvalue of type sign...

Page 56: ...pleRate22050 22050 RC200AudioSampleRate32000 32000 RC200AudioSampleRate44100 44100 RC200AudioSampleRate48000 48000 default Timing 1 clock cycle Description Changes the sample rate of the audio output 5 13 9 Writing to the audio interface extern macro proc RC200AudioOutWrite Left Right Parameters Left Data value of type signed 20 Right Data value of type signed 20 Timing 1 or more clock cycles bloc...

Page 57: ...ingle item of data from the Bluetooth interface and stores it in the lvalue pointed at by DataPtr Note that these are raw bytes from the Bluetooth interface device By default the Bluetooth interface device uses the BlueCore Serial Protocol BCSP from Cambridge Silicon Radio 5 14 4 Writing to the Bluetooth device extern macro proc RC200BluetoothWrite Data Parameters Data Data value of type unsigned ...

Page 58: ...dia card To perform a read or write using logical addressing you need to 1 Call RC200SmartMediaCheckLogicalFormat If this macro returns 1 to indicate failure you need to perform a logical format on the card using the Celoxica FTU2 program 2 Set the address using RC200SmartMediaSetLogicalAddress 3 Call RC200SmartMediaRead or RC200SmartMediaWrite for each byte of data For the last byte of data set t...

Page 59: ...controller stores internally f a SmartMedia device can be determined after a successful call to diaGetMakerCode and es of type unsigned 8 For example unsigned 8 Maker Device ode ia management tasks extern macr oc RC200SmartMediaRun ClockRate ClockRate Clock rate of the clock domain of the call to this macro Does not terminate in normal use Runs the SmartMedia physical layer driver parallel with ot...

Page 60: ...0 clock cycles or more Performs an erase on the entire block set by Address Note that for 16 pages per block 4 8MB cards the blo You can check how many pages there are in a block in your card using RC200SmartMediaIsBlock32Pages column number 5 15 7 Number of pages per block extern macro expr RC200SmartMediaIsBlock32Pages You can determine whether your SmartMedia device has 16 or 32 pages per block...

Page 61: ...address m mat a card for physical addressing using RC200SmartMediaFormat To set a physical e RC200SmartMediaSetAddress Ï For information on how the phy using the PSL refer to the RC200 Hardware and Installation Guide the documentation for your SmartMedia card or http www ssfdc or jp english g for a lo o pr Parameters type unsigned 1 Returns 0 if the card is ss map or 1 if it is not Timing Descript...

Page 62: ...set Note that the operation in the SmartMedia will not terminate unless a read or write and an operation end RC200SmartMediaOperationEnd are performed The macro adjusts automatically for whether the address is in the first half of the page address 256 or the second half of the page 255 address 512 Setting a physical address extern macro proc RC200SmartMediaSetAddress WriteNotRead Address Parameter...

Page 63: ...00SmartMediaGetError Writing to the SmartMedia extern macro proc RC200SmartMediaWrite Data LastData Parameters Data Register value to write of type unsigned 8 LastData Compile time constant to indicate the end of the data Set LastData to 1 to indicate that the last byte of data is being written Timing 390 clock cycles or more including setting the address Description Writes sequential data one byt...

Page 64: ... error in the previous operation and return 0 otherwise 5 16 Ethernet macros Timing of the Ethernet macros is unpredictable since the chip has its own CPU and because of the unpredictable nature of network communications for example a packet could be corrupt 1 Call RC200EthernetRun in parallel with the rest of the read write code 2 Call RC200EthernetEnable 3 Call RC200EthernetReadBegin or RC200Eth...

Page 65: ...Description Takes the Ethernet device out of isolation mode and programs the transmit and receive parameters according to Mode You must call this macro after RC200EthernetRun and before you issue any other commands to the Ethernet chip It must also be run after a call to RC200EthernetDisable to enable access to the Ethernet chip again 5 16 3 Setting the Ethernet mode extern macro expr RC200Etherne...

Page 66: ...and if it is starts the read process and returns destination source status and byte count from the packet header If it times out while waiting for a packet ResultPtr is returned as 1 otherwise it is returned as 0 In this case no further packet read commands should be issued Reading a byte of data from a packet extern macro proc RC200EthernetRead DataPtr ResultPtr Parameters DataPtr Pointer to data...

Page 67: ... MAC address for the packet DataByteCount Data of type unsigned 11 Specifies the number of data bytes to be sent Possible values 64 1518 ResultPtr Pointer to data of type unsigned 1 Returns 1 failure or 0 success Timing At least 100 clock cycles Timing depends on what the chip is doing when the macro is called Description Starts a Packet Write operation to send data to the Ethernet device and from...

Page 68: ... type unsigned 1 Returns 1 failure packet has not been transmitted or 0 success Timing 45 clock cycles to 5ms timeout depending on speed of response of Ethernet device Description Completes the process of writing a packet by commanding the Ethernet device to send it onto the network and waiting for completion or timeout You must call this macro after all the data has been written to a packet 5 17 ...

Page 69: ...ks for the CLPD interface You must run this macro in parallel with accesses to the CPLD 5 18 2 Enabling the CPLD extern macro proc RC200CPLDEnable Parameters None Timing 2 cycles if CPLD is ready for use otherwise undetermined Description You need to call this macro in parallel with RC200CPLDRun and before accesses to the CPLD The macro waits until the CPLD is ready and then sets the CPLD internal...

Page 70: ...endProtocolRead DataPtr c RC20 Paramete None Timing 1 clock cycle Enables the Send Protocol driver You cannot use this at the same time as the RC200 SmartMedia macros You need to call RC200CPLDRun and RC200CPLDEnable before calling this macro You must call this macro before a 5 19 2 Disabling the Send Protocol driver extern macr endPro Paramete None Timing 1 clock cycle Des 5 19 3 Writing data to ...

Page 71: ...e of data from the host PC and writes it to the FPGA This macro will block if the host has not sent any data to be read You must call RC200SendProtocolEnable before using this macro 5 20 Expansion port pins extern macro expr RC200ExpansionPins Description Pin list for the ATA style expansion connector on the RC200 You can use this to create your own interface to this connector www celoxica com Pag...

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Page 73: ...sabling 67 enabling 66 mode 67 reading from 67 resetting 67 writing to 69 expansion port pins 30 73 Expert RC200 36 F FPGA 70 72 operation modes 19 reading data from host PCPC 21 73 reading from 21 73 reconfiguring 19 20 70 register map in CPLD 15 SmartMedia access 22 writing data to FPGA 20 73 writing data to host PC 21 73 H header files 36 J JTAG chain 33 K keyboard 43 reading from 43 writing to...

Page 74: ...ead 68 RC200EthernetReadBegin 67 RC200EthernetReadEnd 68 RC200EthernetRun 66 RC200EthernetWrite 69 RC200EthernetWriteBegin 69 RC200EthernetWriteEnd 70 RC200ExpansionPins 73 RC200LED Write 38 RC200LEDWriteMask 38 RC200PL1RAM Read 42 RC200PL1RAM Run 41 RC200PL1RAM SetReadAddress 40 41 RC200PL1RAM SetWriteAddress 41 RC200PL1RAM Write 42 RC200PS2KeyboardRead 43 RC200PS2KeyboardRun 43 RC200PS2KeyboardW...

Page 75: ...0 signals 15 16 ALE signal 15 16 CCLK signal 14 CLE signal 15 16 CLKUSER 24 37 DONE signal 16 EXPCLK0 37 EXPCLK1 37 nBUSY signal 16 nCS signal 14 15 16 nINIT signal 14 16 nPROG signal 14 16 nRDWR signal 14 PnCS signal 14 SmartMedia Detect signal 16 SmartMedia 22 address structure 62 checking for errors 63 65 completing a read or write 63 65 configuring the FPGA 20 connections to the CPLD 22 device...

Page 76: ...RC200 203 PSL reference TFT 28 writing data 50 www celoxica com Page 76 ...

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