CDB43198-GBK
16
DS1156DB1
2.7.1
Current Measurement Headers
The table below shows a list of current measurement headers and the associated rails. To measure current of a particular
voltage rail, remove the jumper and place a current probe across the pins of the header.
Table 9 Current Measurement Headers
Header
Voltage Rail
VP-QFN
VP-QFN
VP-CSP
VP-CSP
VA
VA
VCP
VCP
VL
VL
VD
VD
2.7.2
Push-Button Resets (Revision B only)
There are 2 SPST push buttons for resetting the board in case something enters an unknown state. There are 2 buttons,
S1 for a system-wide reset, and S2 for a DAC-only reset.
Table 10 Push-Button Resets
Button Name
Descriptor
Reset Tied To
S1
SYS_RESET
CS43198-CSP, CS43198-QFN, CS8422 Smart Codec, USB MCU,USB HUB, XMOS
S2
DAC_RESET
CS43198-CSP, CS43198-QFN
2.8 Codec MCLK Selection
The MCLK input to the smart codec can come either from the on-board 24.576 MHz clock oscillator, a 22.579 MHz clock
oscillator, MCLK1 from ASP(J25), MCLK2 from XSP(J26) or from the CLKOUT pin on the DAC or the MCLK output from
an external audio source. The selection is controlled by WISCE.
Figure 11 CODEC MCLK Selection
2.9 Clock Sources
The CDB43198 Board has 2 separate onboard 22.5792 MHz crystals to act as the MCLK source for the CS43198 CSP
and QFN DUTs. In addition to the crystal, the board also provides an option to supply MCLK either from an external
source, such as a function generator. These oscillators are Y1 (CSP) and Y2(QFN). By default, these crystals are
enabled. In order to use an external clock source, you need to depopulate R11(CSP) and R28(QFN) and solder in a 0-
Ω
resistor in R10(CSP) and R39(QFN). To enable the external MCLK, you need to select it in the IO expander in WISCE.
Figure 12 EXT MCLK Selection
