CDB43198-GBK
DS1156DB1
7
2.2 Digital Audio Input
2.2.1
Serial Audio I/O Headers
Headers J25 and J26, labeled ASP and XSP respectively, provide an interface for serial audio clocks and data. The
source of the clocks and data can be an external audio source such as a Audio Precision audio analyzer. The header
signals are described in the table below. The logic level on these pins is selectable by jumping J28 to 3.3 V or 1.8V.
Table 1 Serial Audio Header Pinout
Reference Designator
Pins
Pin Designation
Direction
Description
J25
7
MCLK
I/O
Master clock
5
SCLK
I/O
Bit clock
3
LRCLK
I/O
Frame clock
1
RXDAT
Input
Serial data
2,4,6,8
Ground
Ground reference
Board ground
J26
7
MCLK
I/O
Master clock
5
SCLK
I/O
Bit clock
3
LRCLK
I/O
Frame clock
1
RXDAT
Input
Serial data
2,4,6,8
Ground
Ground reference
Board ground
Audio signals to/from these headers are routed to/from the CS43198 using voltage-level translation buffers. The direction
of clock and data through these buffers is controlled using on-board TCA6424 I/O Expander IC. U9, U12, and U15
translate the signals on J25 and J26 from a voltage of 3.3 V or 1.8 V to the operational voltage of 1.8 V. The ASP signals
are then fed into J24, while the XSP signals are fed into J44. These 3x3 pin headers are for passing the I
2
S data from the
CS8422 S/PDIF transceiver to the DUTs.
To avoid the latency caused by buffers for higher clock frequencies like 352.8 kHz or 384 kHz, the user can connect the
external audio source directly to pins on headers J24 and J44. The pinouts for headers J24 and J44 are shown in the
following tables.
Table 2 Pinouts for Header J24
Pin #
Signal
1
SCLK1 from Buffer
2
SCLK1 to DAC
4
LRCLK1 from Buffer
5
LRCLK1 to DAC
7
SDIN1 from Buffer
8
SDIN1 to DAC
3,6,9
Ground
Table 3 Pinouts for Header J44
Pin #
Signal
1
SCLK2 from Buffer
2
SCLK2 to DAC
4
LRCLK2 from Buffer
5
LRCLK2 to DAC
7
SDIN2 from Buffer
8
SDIN2 to DAC
3,6,9
Ground
