DS632F1
13
CS44800
SWITCHING CHARACTERISTICS - DAI INTERFACE
(VD = 2.5 V, VDX = VDP = VLC = 3.3 V, VLS = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLS.)
15. After powering up, the CS44800, RST should be held low until after the power supplies and clocks are set-
tled.
16. See
Table 1 on page 26
for suggested MCLK frequencies.
17. Max DAI sample rate is 96 kHz for One Line and TDM modes of operation.
Parameters
Symbol
Min
Max
Units
RST pin Low Pulse Width
1
-
ms
DAI_MCLK Duty Cycle
40
60
%
DAI_SCLK Duty Cycle
45
55
%
DAI_LRCK Duty Cycle
45
55
%
DAI Sample Rate
F
s
32
192
kHz
DAI_SDIN Setup Time Before DAI_SCLK Rising Edge
t
ds
10
-
ns
DAI_SDIN Hold Time After DAI_SCLK Rising Edge
t
dh
10
-
ns
DAI_SCLK High Time
t
sckh
20
-
ns
DAI_SCLK Low Time
t
sckl
20
-
ns
DAI_LRCK Setup Time Before DAI_SCLK Rising Edge
t
lrcks
25
-
ns
DAI_SCLK Rising Edge Before DAI_LRCK Edge
t
lrckd
25
-
ns
s ck h
s c k l
t
t
D A I_ S D IN x
lrc k s
t
lrc k d
t
D A I_ S C L K
D A I_ L R C K
d s
t
d h
t
Figure 6. Serial Audio Interface Timing
Figure 7. Serial Audio Interface Timing - TDM Mode
sckh
sckl
t
t
DAI_SDIN1
dh
t
ds
t
lrcks
t
lrckd
t
DAI_SCLK
(input)
DAI_LRCK
(input)
lrcks
t
MSB
MSB-1
