24
DS726PP2
CS4525
I²C CONTROL PORT SWITCHING SPECIFICATIONS
AGND = DGND = PGND = 0 V; T
A
= 25°C; VD = 3.3 V; Inputs: Logic 0 = DGND; Logic 1 = VD; SDA C
L
= 30 pF.
Notes:
16. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
Parameter Symbol
Min
Max
Unit
SCL Clock Frequency
f
scl
-
100
kHz
RST Rising Edge to Start
t
irs
500
-
ns
Bus Free Time Between Transmissions
t
buf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0
-
µs
Clock Low time
t
low
4.7
-
µs
Clock High Time
t
high
4.0
-
µs
Setup Time for Repeated Start Condition
t
sust
4.7
-
µs
SDA Hold Time from SCL Falling
t
hdd
10
-
ns
SDA Setup time to SCL Rising
t
sud
250
-
ns
Rise Time of SCL and SDA
t
rc
-
1
µs
Fall Time SCL and SDA
t
fc
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
µs
Acknowledge Delay from SCL Falling
t
ack
300
1000
ns
t
buf
t
hdst
t
hdst
t
low
t r
t f
t
hdd
t
high
t sud
t sust
t susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
t
irs
RST
Figure 11. Control Port Timing - I²C
