DS726PP2
65
CS4525
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition. (Optional.)
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
7. PCB LAYOUT CONSIDERATIONS
7.1
Power Supply, Grounding
As with any high-resolution converter, the CS4525 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS4525 as pos-
sible. The lowest value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS4525 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+
and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path
from FILT+ and AGND. The CRD4525 reference design demonstrates the optimum layout and power sup-
ply arrangements.
7.2
QFN Thermal Pad
The CS4525 is available in a compact QFN package. The underside of the QFN package reveals a large
metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
thermal vias should be used to connect this copper pad to one or more larger ground planes on other PCB
layers. The CRD4525 reference design demonstrates the optimum thermal pad and via configuration.
For more information concerning thermal considerations of QFN packages, please refer to Cirrus Logic ap-
plication note AN315.
