DS726PP2
69
CS4525
9. REGISTER DESCRIPTIONS
All registers are read/write unless otherwise stated. All “Reserved” bits must maintain their default state.
9.1
Clock Configuration (Address 01h)
9.1.1
SYS_CLK Output Enable (EnSysClk)
Default = 1
Function:
This bit controls the output driver for the SYS_CLK signal. When cleared, the output driver is disabled and
the SYS_CLK pin is high-impedance. When set, the output driver is enabled.
If the SYS_CLK output is unused, this bit should be set to ‘0’b to disable the driver.
9.1.2
SYS_CLK Output Divider (DivSysClk)
Default = 0
Function:
This bit determines the divider for the XTAL clock signal for generating the SYS_CLK signal.
This divider is only available if the clock source is an external crystal attached to XTI/XTO and the
SYS_CLK output is enabled.
9.1.3
Clock Frequency (ClkFreq[1:0])
Default = 01
Function:
These bits must be set to identify the nominal clock frequency of the crystal attached to the XTI/XTO pins
or that of the input SYS_CLK signal. See the
table on
and the
SYS_CLK Switching Specifications
table on
for complete input frequency range specifications.
7
6
5
4
3
2
1
0
EnSysClk
DivSysClk
ClkFreq1
ClkFreq0
HP/MutePol
HP/Mute
PhaseShift
FreqShift
EnSysClk Setting
Output Driver State
0 .......................................... Output driver disabled.
1 .......................................... Output driver enabled.
DivSysClk Setting
SYS_CLK Output Frequency
0 .......................................... F
SYS_CLK
= F
XTAL
1 .......................................... F
SYS_CLK
= F
XTAL
/2
ClkFreq[1:0] Setting
Specified Nominal Input Clock Frequency
00 ........................................ 18.432 MHz
01 ........................................ 24.576 MHz
10 ........................................ 27.000 MHz
11......................................... Reserved
