3-11
Copyright 2009 Cirrus Logic, Inc.
DS734UM7
Serial Control Port Configuration
CS485xx Hardware User’s Manual
3.2.2.4.1 I
2
C Read Protocol Procedure
1. An I
2
C
read transaction is initiated by CS485xx driving SCP_IRQ low, signaling that it has data to be
read.
2. The master responds by sending an I
2
C
Start condition which is SCP_SDA going low while SCP_CLK
is held high.
3. This is followed by a 7-bit address and the read/write bit set high for a read. So, the master should
send 0x81. The 0x81 byte represents the 7-bit I
2
C address 1000000b, and the least significant bit set
to ‘1’, designates a read.
4. After the address byte, the master must release the data line and provide a ninth clock for the
CS485xx DSP (slave) to acknowledge (ACK) receipt of the byte. The CS485xx will drive the data line
low during the ninth clock to acknowledge. If for some reason CS485xx does not acknowledge
(NACK), it means that the communications channel has been corrupted and the CS485xx should be
re-booted. A NACK should never happen here.
5. The data is ready to be clocked out on the SCP_SDA line at this point. Data clocked out by the host is
valid on the rising edge of SCP_CLK and data transitions occur just after the falling edge of SCP_CLK.
6. After the CS485xx has written the byte to the master on the SCP_SDA line, it will release the
SCP_SDA line. If the master has more bytes in the 4-byte word to read, then proceed to step 7. If the
master is finished reading all bytes of the 4-byte word, then proceed to step 8.
7. The master should drive the SCP_SDA line low for the 9
th
SCP_CLK clock to acknowledge (ACK) that
the byte was received from the CS485xx. The master should then return to step 5 to read another byte
of the 4-byte word.
8. If SCP_IRQ is still low after reading a 4-byte word, proceed to step 7. If SCP_IRQ has risen, proceed
to step 9.
9. The master should let the SCP_SDA line stay high for the 9th SCP_CLK clock as a no-acknowledge
(NACK) to CS485xx. This, followed by an I
2
C stop condition (SCP_SDA driven high, while SCP_CLK
is high) signals an end of read to CS485xx. See the next section,
"SCP_IRQ Behavior"
for the an in-
depth explanation of SCP_IRQ.
3.2.2.4.2 SCP_IRQ Behavior
The SCP_IRQ signal is not part of the I
2
C protocol, but is provided so that the slave can signal that it has
data to be read. A high-to-low transition on SCP_IRQ indicates to the master that the slave has data to be
read. When a master detects a high-to-low transition on SCP_IRQ, it should send a Start condition and
begin reading data from the slave.
SCP_IRQ is guaranteed to remain low (once it has gone low), until the falling edge of SCP_CLK for the last
bit of the last byte to be transferred out of CS485xx (i.e. the rising edge of SCP_CLK before the ACK). If
there is no more data to be transferred, SCP_IRQ will go high at this point. After going high, SCP_IRQ is
guaranteed to stay high until the next rising edge of SCP_CLK (i.e. it will stay high until the rising edge of
SCP_CLK for the ACK/NACK bit).
This end-of-transfer condition signals the master to end the read transaction by clocking the last data bit out
of CS485xx and then sending a NACK to CS485xx to signal that the read sequence is over. At this point, the
master should send an I
2
C
stop condition to complete the read sequence. If SCP_IRQ is still low after the
rising edge of SCP_CLK on the last data bit of the current byte, the master should send an acknowledge and
continue reading data from the serial control port. It should be noted that all data should be read out of the
serial control port during one cycle or a loss of data will occur. In other words, all data should be read out of
the chip until SCP_IRQ signals the last byte by going high.
