Clocking
CS485xx Hardware User’s Manual
DS734UM7
Copyright 2009 Cirrus Logic, Inc.
9-12
9.2.3 PLL
The internal phase locked loop (PLL) of the CS485xx requires an external current reference resistor. The
resistor is used to calibrate the PLL and must meet the tolerances specified below. The layout topology is
shown
Table 9-9
. Care should be taken when laying out the current sense circuitry to minimize trace lengths
between the DSP and resistor, and to keep high-frequency signals away from the resistor. Any noise
coupled onto the these traces will be directly coupled into the PLL, which could affect performance. Please
Table 9-5
and
Table 9-6
for pin numbers and external component value.
Figure 9-9. PLL Filter Topology
9.3 Clocking
The CS485xx incorporates a programmable phase locked loop (PLL) clock synthesizer. The PLL takes an
input reference clock and produces all the clocks required to run the DSP and peripherals.
The CS485xx has a built-in crystal oscillator circuit. See
Chapter 7, "Crystal Oscillator and System
Clocking"
for more details on system clocking and the crystal oscillator.
9.4 Control
The CS485xx supports 2 control interface protocols (SPI and I
2
C), one slave mode for each protocol, and
multiple master modes.
Table 9-5. PLL Filter Pins
LQFP-48
Pin #
Pin Name
Pin Type
Pin Description
47
PLL_REF_RES
Input
Current Reference Resistor for
PLL filter
Table 9-6. Reference PLL Component Values
Symbol
Reference Value
R1
5.1 k
Ω,
1%
PLL_REF_RES
GNDA
CS48500
R1
VDDA
3.3V
Bead
10u
0.1u
