CDB4923 CDB49300
DS262DB2
13
As mentioned above, many of the PLD’s I/O pins
are tri-stated. The complete list of tri-stated pins
for full external mode (PLD Mode 0) can be found
in Table 6. The complete list of tri-stated pins for
external control mode (PLD Mode 1) can be found
in Table 7.
By design, the clocking signals present at the
MCLK, LRCLK, and SCLK pins of the
CS492x/CS493xx are used to drive both the audio
input and output circuitry for the rest of the
CDB4923/300 as shown in Figure 3. This means
that the S/PDIF input, S/PDIF output, analog out-
put and analog input continue to function in the
EXTERNAL modes. The user should only drive
audio clocks in PLD Mode 0. PLD Mode 1 derives
audio clocks from the CS8414.
The three clocking configurations that the user
should be aware of when using PLD Mode 0 are:
•
DSP is slave to all audio clocks - user drives
MCLK/SCLK/LRCLK
•
DSP masters LRCLK/SCLK - user drives
MCLK
•
DSP masters MCLK/LRCLK/SCLK - user
drives no audio clocks
Only when the correct clocking is present on the
23MCLK, 23LRCLK, and 23SCLK pins (J12),
processed audio can be heard on the analog outputs
(J13 - J20) and the digital outputs (J45 - J47). The
analog outputs J13-J20 can be found in Figure 12,
and the digital outputs can be found in Figure 13.
The information in Table 9 summarizes the opera-
tion of switch S3. The table shows the data routing
configuration, the MCLK source, and the method
of board control. This is intended as a quick refer-
ence and can also be found in Appendix J: Switch
Summary.
Pin Name
Pin
Number
Pin Name
Pin
Number
MCLK
44
DATA0
17
CMPCLK
28
DATA1
16
CMPREQ
29
DATA2
15
CMPDAT
27
DATA3
14
SCLKN1
25
DATA4
11
SLRCLKN1
26
DATA5
10
SDATAN1
22
DATA6
9
RESET
36
DATA7
8
RD
5
A1, CDIN
6
WR
4
A0, SCCLK
7
EXTMEM
21
SCPDIO
19
CS
18
Table 6. DSP Pins Tri-Stated by U11 in PLD Mode 0
Pin Name
Pin
Number
Pin Name
Pin
Number
RESET
36
DATA0
17
RD
5
DATA1
16
WR
4
DATA2
15
A1, CDIN
6
DATA3
14
A0, SCCLK
7
DATA4
11
SCPDIO
19
DATA5
10
CS
18
DATA6
9
DATA7
8
Table 7. DSP Pins Tri-Stated by U11 in PLD Mode 1
MCLK
Source
Description
J12
The user must provide an oversampling clock on
the 23MCLK pin of stake header J12. (NOTE:
This clock signal must be +3.3 V logic when
using CS493xx)
CS8414 The CS8414 (U13) derives the sampling fre-
quency (Fs) from an incoming S/PDIF stream
and masters a 256 Fs MCLK
DSP
The DSP (U1) masters MCLK, generally when
using broadcast application code
Table 8. Clocking Descriptions
Summary of Contents for CS492 Series
Page 18: ...CDB4923 CDB49300 18 DS262DB2 9 APPENDIX A SCHEMATICS Figure 4 CS492x CS493xx ...
Page 19: ...CDB4923 CDB49300 DS262DB2 19 Figure 5 System Power ...
Page 20: ...CDB4923 CDB49300 20 DS262DB2 Figure 6 PC Interface ...
Page 21: ...CDB4923 CDB49300 DS262DB2 21 Figure 7 Control Logic ...
Page 22: ...CDB4923 CDB49300 22 DS262DB2 Figure 8 Clocking ...
Page 23: ...CDB4923 CDB49300 DS262DB2 23 Figure 9 Analog Input ...
Page 24: ...CDB4923 CDB49300 24 DS262DB2 Figure 10 Digital Input ...
Page 25: ...CDB4923 CDB49300 DS262DB2 25 Figure 11 D A Converters ...
Page 26: ...CDB4923 CDB49300 26 DS262DB2 Figure 12 Analog Output ...
Page 27: ...CDB4923 CDB49300 DS262DB2 27 Figure 13 Digital Output ...
Page 28: ...CDB4923 CDB49300 28 DS262DB2 Figure 14 Top Layer ...
Page 29: ...CDB4923 CDB49300 DS262DB2 29 Figure 15 Bottom Layer ...
Page 30: ...CDB4923 CDB49300 30 DS262DB2 Figure 16 SSTOP ...
Page 31: ...CDB4923 CDB49300 DS262DB2 31 Figure 17 ASYSTOP ...
Page 32: ...CDB4923 CDB49300 32 DS262DB2 Figure 18 Layer 2 ...
Page 33: ...CDB4923 CDB49300 DS262DB2 33 Figure 19 Layer 3 ...
Page 49: ... Notes ...
Page 50: ......
