Cirrus Logic CS492 Series Manual Download

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CDB4923 CDB49300

DS262DB2

ally, both jumpers of J37 should be set to the OSC
position. In this clocking configuration you should
not use any modes which list OSC/PLL as the
MCLK source while Y1 is 27 MHz.

In order to use the 12.288 MHz oscillator directly,
Y1 should be populated with the 12.288 MHz os-
cillator included with the CDB4923/300 package,
and both jumpers of J37 should be set to the OSC
position. The 12.288 MHz oscillator can be used
with those PLD modes naming OSC/PLL as the
MCLK source, as 12.288 MHz is a standard 256Fs
oversampling frequency (256 * 48 kHz).

The choice of 12.288 MHz or 27 MHz is applica-
tion code dependent. Applications dealing with
IEC61937 packed compressed audio generally re-
quire a 12.288 MHz input, while broadcast applica-
tions typically require a 27 MHz input. Check the
relevant application code user’s guide (AN120-
AN123, AN140 or AN161-AN163) for details on
DSP CLKIN frequency.

If the external PLL is to be used, then Y1 must be
populated with a 27 MHz oscillator. The jumpers
of J37 should both be placed in the PLL position.
The CLKIN pin of the DSP will now be driven with
the processor clock (PCLK) output of U26. The
processor clock (PCLK) output can be configured
to generate either a many different frequencies,
based upon the configuration of jumpers J67, J68,
and J72 as listed in Table 12.

When using the external PLL to generate the DSP
clock, the CLKSEL pin (J1) of the
CS492x/CS493xx is typically set to ‘EXT CLK’.

6.2

MCLK

The system MCLK on the CDB4923/300 can come
from four different sources when using a PROVID-
ED mode. Some PLD modes use the MCLK gener-
ated by the CS8414 S/PDIF receiver (U13) when
there is an incoming S/PDIF stream. In PLD mode
2, the DSP generates MCLK when it is decoding a
compressed bit stream delivered by the PC. Some

modes can select between an MCLK which is sim-
ply the frequency of the on-board oscillator (Y1),
or a programmable MCLK generated by the exter-
nal PLL (U26).

The source of MCLK is dependent upon the PLD
mode and is indicated by the ‘MCLK SOURCE’
column of Table 9 a nd Table 24.

U26 is a discrete PLL which can generate many
different audio frequencies in addition to the pro-
cessor clock discussed above. The frequency of the
audio clock is controlled by the states of the AS1
and AS0 pins which are set with jumpers J70 and
J71. The available audio clock frequencies can be
used to support many different sampling frequen-
cies, depending on the desired MCLK ratio. Table
13 enumerates all possible MCLK frequencies for
the external PLL.

6.3

LRCLK and SCLK

LRCLK and SCLK are assumed to be generated by
the DSP in all cases. The audio clocking diagram
shown in Figure 3, illustrates the clocking scheme
of the CDB4923/300. If it is necessary to provide a
complete slave mode for the DSP, please contact
the factory for details on how to properly configure
the CDB4923/300.

PCLK Frequency

J72

J67

J68

33.33 MHz

54 MHz

66.66 MHz

80 MHz

32 MHz

81 MHz

50 MHz

40 MHz