CS5374
CS5374
33
regulator output, with additional power supply
bulk capacitance placed among the analog compo-
nent route if space permits.
8.4 PCB Layers and Routing
The CS5374 is a high-performance device, and
special care must be taken to ensure power and
ground routing is correct. Power can be supplied ei-
ther through dedicated power planes or routed trac-
es. When routing power traces, it is recommended
to use a “star” routing scheme with the star point ei-
ther at the voltage regulator output or at a local
power supply bulk capacitor.
It is also recommended to dedicate a full PCB layer
to a solid ground plane, without splits or routing.
All bypass capacitors should connect between the
power supply circuit and the solid ground plane as
near as possible to the device power supply pins.
The CS5374 analog signals are differentially rout-
ed and do not normally require connection to a sep-
arate analog ground. However, if a separate analog
ground is required, it should be routed using a
“star” routing scheme on a separate layer from the
solid ground plane and connected to the ground
plane only at a single point. Be sure all active de-
vices and passive components connected to the
separate analog ground are included in the “star”
route to ensure sensitive analog currents do not re-
turn through the ground plane.
8.5 Power Supply Rejection
Power supply rejection of the CS5374 is frequency
dependent. The CS5376A digital filter fully rejects
power supply noise for frequencies above the se-
lected digital filter corner frequency. Power supply
noise frequencies between DC and the digital filter
corner frequency are rejected as specified in the
“Power Supply Characteristics” on page 13
.
8.6 SCR Latch-up Considerations
It is recommended to connect the VA– power sup-
ply to system ground (GND) through a reverse-bi-
ased Schottky diode. At power up, if the VA+
power supply ramps up before the VA– supply is
established, the VA- pin voltage could be pulled
above ground potential through the CS5374 de-
vice. If the VA– supply is pulled 0.7 V or more
above GND, SCR latch-up can occur. A reverse-bi-
ased Schottky diode will clamp the VA– voltage a
maximum of 0.3 V above ground to ensure SCR
latch-up does not occur at power up.
For similar reasons, care should be taken to connect
the CS5374 thermal pad on the bottom of the pack-
age to VA–, not system ground (GND), since it in-
ternally connects to VA– and is expected to be the
most negative applied voltage.
8.7 DC-DC Converters
Many low-frequency measurement systems are
battery powered and utilize DC-DC converters to
efficiently generate power supply voltages. To
minimize interference effects, operate the DC-DC
converter at a frequency which is rejected by the
digital filter, or operate it synchronous to the
MCLK rate.
A synchronous DC-DC converter whose operating
frequency is derived from MCLK will theoretically
minimize the potential for “beat frequencies” to ap-
pear in the
measurement bandwidth. However this
requires the source clock to remain jitter free with-
in the DC-DC converter circuitry. If clock jitter can
occur within the DC-DC converter (as in a PLL-
based architecture), it’s better to use a non-syn-
chronous DC-DC converter whose switching fre-
quency is rejected by the digital filter.
During PCB layout, do not place high-current DC-
DC converters near sensitive analog components.
Carefully routing a separate DC-DC “star” ground
will help isolate noisy switching currents away
from the sensitive analog components.
