Cirrus Logic EP93 Series User Manual Download

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9-36

DS785UM1

1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide

9.2.3.14 Transmit Descriptor Data/Status Flow

Figure 9-17. Transmit Descriptor Data/Status Flow

SoftWare

HardWare

[ LAN]

SoftWare

Reset

Initialize

Tx Descriptor

and Status

Queues

Write TxDEQ

with valid

descriptor count

Idle

Read Tx

Descriptors

Send Frame 0

Send Frame 1

Write TxDEQ

with valid

descriptor count

Write TxDEQ

with valid

descriptor count

Random timing between
Write TxEnq steps

Send Frame 2

Write

Tx Status

Process

Tx Status

Read Tx

Data

Read Tx

Descriptors

Read Tx

Descriptors

Read Tx

Data

Read Tx

Data

Read Tx

Data

Write

Tx Status

Write

Tx Status

Process

Tx Status

Process

Tx Status

Pro LAN

Summary of Contents for EP93 Series

Page 2: ...ISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS CIRRUS PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WAR RANTED FOR USE IN AIRCRAFT SYSTEMS MILITARY APPLICATIONS PRODUCTS SURGICALLY IMPLANTED INTO THE BODY LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS INCLUDING MEDICAL DEVICES AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURI...

Page 3: ...osts 1 9 1 4 7 Multiple Booting Mechanisms Increase Flexibility 1 9 1 4 8 Abundant General Purpose I Os Build Flexible Systems 1 9 1 4 9 General Purpose Memory Interface SDRAM SRAM ROM FLASH 1 9 1 4 10 12 Bit Analog to Digital Converter ADC Provides an Integrated Touch Screen Interface or General ADC Functionality 1 10 1 4 11 Raster Analog LCD Controller 1 10 1 4 12 Graphics Accelerator 1 10 1 4 1...

Page 4: ...8 3 2 2 Example 2 3 9 3 2 2 1 C Code 3 9 3 2 2 2 MaverickCrunch Assembly Language Instructions 3 9 3 3 DSPSC Register 3 10 3 4 ARM Co Processor Instruction Format 3 14 3 5 Instruction Set for the MaverickCrunch Co Processor 3 17 3 5 1 Load and Store Instructions 3 21 3 5 2 Move Instructions 3 24 3 5 3 Accumulator and DSPSC Move Instructions 3 27 3 5 4 Copy and Conversion Instructions 3 31 3 5 5 Sh...

Page 5: ...pter 7 Raster Engine With Analog LCD Integrated Timing and Interface 7 1 7 1 Introduction 7 1 7 2 Features 7 3 7 3 Raster Engine Features Overview 7 3 7 3 1 Hardware Blinking 7 3 7 3 2 Color Look Up Tables 7 4 7 3 3 Grayscale Color Generation for Monochrome Passive Low Color Displays 7 4 7 3 4 Frame Buffer Organization 7 4 7 3 5 Frame Buffer Memory Size 7 6 7 3 6 Pulse Width Modulated Brightness 7...

Page 6: ... 8 2 8 2 1 2 Logical Mask 8 2 8 2 1 3 Logical Destination 8 2 8 2 1 4 Operation Precedence 8 2 8 2 2 Remapping 8 3 8 2 3 Block Fills 8 3 8 2 4 Packed Memory Transfer 8 3 8 3 Line Draws 8 3 8 3 1 Breshenham Line Draws 8 4 8 3 2 Pixel Step Line Draws 8 4 8 4 Memory Organization for Graphics Accelerator 8 4 8 4 1 Memory Organization for 1 Bit Per Pixel bpp 8 5 8 4 2 Memory Organization for 4 Bits Per...

Page 7: ...Rx Missed and Tx Collision Counters 9 11 9 1 4 11 Accessing the MII 9 11 9 2 Descriptor Processor 9 13 9 2 1 Receive Descriptor Processor Queues 9 13 9 2 2 Receive Descriptor Queue 9 13 9 2 3 Receive Status Queue 9 16 9 2 3 1 Receive Status Format 9 18 9 2 3 2 Receive Flow 9 21 9 2 3 3 Receive Errors 9 22 9 2 3 4 Receive Descriptor Data Status Flow 9 23 9 2 3 5 Receive Descriptor Example 9 24 9 2 ...

Page 8: ...cription 10 10 10 1 10 1 M2M DMA Control Finite State Machine 10 10 10 1 10 2 M2M Buffer Control Finite State Machine 10 12 10 1 10 3 Data Transfer Initiation 10 13 10 1 10 4 Data Transfer Termination 10 15 10 1 10 5 Memory Block Transfer 10 16 10 1 10 6 Bandwidth Control 10 16 10 1 10 7 External DMA Request DREQ Mode 10 16 10 1 11 DMA Data Transfer Size Determination 10 17 10 1 11 1 Software Init...

Page 9: ...CMCIA Configuration Registers EP9315 Processor Only 12 13 Chapter 13 SDRAM SyncROM and SyncFLASH Controller 13 1 13 1 Introduction 13 1 13 2 Booting from SyncROM or SyncFLASH 13 1 13 3 Address Pin Usage 13 3 13 4 SDRAM Initialization 13 4 13 5 Programming Mode Register SDRAM Or SyncROM Device 13 6 13 6 SDRAM Self Refresh 13 8 13 6 1 Entering Self Refresh Mode 13 8 13 6 2 Exiting Self Refresh Mode ...

Page 10: ...A 14 14 14 4 9 Writing Configuration Registers 14 14 14 5 UART1 Package Dependency 14 14 14 5 1 Clocking Requirements 14 15 14 5 2 Bus Bandwidth Requirements 14 16 14 1 Registers 14 17 Chapter 15 UART2 15 1 15 1 Introduction 15 1 15 2 IrDA SIR Block 15 1 15 2 1 IrDA SIR Encoder decoder Functional Description 15 1 15 2 1 1 IrDA SIR Transmit Encoder 15 2 15 2 1 2 IrDA SIR Receive Decoder 15 2 15 2 2...

Page 11: ...Features 17 13 17 5 1 Introduction 17 14 17 5 1 1 4PPM Modulation 17 14 17 5 1 2 4 0 Mbps FIR Frame Format 17 15 17 5 2 Functional Description 17 17 17 5 2 1 Baud Rate Generation 17 17 17 5 2 2 Receive Operation 17 18 17 5 2 3 Transmit Operation 17 19 17 5 3 IrDA Connectivity 17 20 17 5 4 IrDA Integration Information 17 21 17 5 4 1 Enabling Infrared Modes 17 21 17 5 4 2 Clocking Requirements 17 21...

Page 12: ...1 7 21 5 I2 S Bit Clock Rate Generation 21 9 21 5 1 Example of the Bit Clock Generation 21 9 21 5 2 Example of Right Justified LRCK format 21 10 21 6 Interrupts 21 10 21 7 Registers 21 12 21 7 1 I2S TX Registers 21 12 21 7 2 I2 S RX Registers 21 19 21 7 3 I2 S Configuration and Status Registers 21 25 21 7 4 I2S Global Status Registers 21 29 Chapter 22 AC 97 Controller 22 1 22 1 Introduction 22 1 2...

Page 13: ...ion 24 1 24 2 Theory of Operation 24 1 24 2 1 PWM Programming Examples 24 2 24 2 1 1 Example 24 2 24 2 1 2 Static Programming PWM is Not Running Example 24 2 24 2 1 3 Dynamic Programming PWM is Running Example 24 3 24 2 2 Programming Rules 24 3 24 3 Registers 24 3 Chapter 25 Analog Touch Screen Interface 25 1 25 1 Introduction 25 1 25 2 Touch Screen Controller Operation 25 1 25 2 1 Touch Screen Sc...

Page 14: ...tem Configuration Constraints 27 9 27 2 8 2 Bus Bandwidth Requirements 27 9 27 3 Registers 27 10 Chapter 28 GPIO Interface 28 1 28 1 Introduction 28 1 28 1 1 Memory Map 28 3 28 1 2 Functional Description 28 3 28 1 3 Reset 28 5 28 1 4 GPIO Pin Map 28 6 28 2 Registers 28 9 Chapter 29 Security 29 1 29 1 Introduction 29 1 29 2 Features 29 1 29 3 Contact Information 29 1 29 4 Registers 29 2 Chapter 30 ...

Page 15: ...an Video Signals 7 29 Figure 7 10 Interlaced Video Signals 7 30 Figure 9 1 1 10 100 Mbps Ethernet LAN Controller Block Diagram 9 1 Figure 9 2 Ethernet Frame Packet Format Type II only 9 4 Figure 9 3 Packet Transmission Process 9 5 Figure 9 4 Carrier Deference State Diagram 9 6 Figure 9 5 Data Bit Transmission Order 9 8 Figure 9 6 CRC Logic 9 9 Figure 9 7 Receive Descriptor Format and Data Fragment...

Page 16: ...ple 17 9 Figure 17 2 4PPM Modulation Encoding 17 14 Figure 17 3 4PPM Modulation Example 17 15 Figure 17 4 IrDA 4 0 Mbps Transmission Format 17 15 Figure 21 1 Architectural Overview of the I2 S Controller 21 1 Figure 21 2 Bit Clock Generation Example 21 10 Figure 21 3 Frame Format for Right Justified Data 21 10 Figure 23 1 Texas Instruments Synchronous Serial Frame Format Single Transfer 23 4 Figur...

Page 17: ...nal Connections Within the Standard GPIO Port Control Logic Ports C D E G H 28 4 Figure 28 3 Signal Connections Within the Enhanced GPIO Port Control Logic Ports A B F 28 5 Tables Table P 1 Frequency Package Applicable EP93xx Processor P 1 Table P 2 Chapter Number and Function Applicable EP93xx Processor P 1 Table 1 1 EP93xx Maximum Clock Rates Package Type and Number of Balls 1 1 Table 1 2 EP93xx...

Page 18: ...riority Order for AHB Arbiter 5 23 Table 5 7 Audio Interfaces Pin Assignment 5 26 Table 6 1 Interrupt Configuration 6 3 Table 6 2 VICx Register Summary 6 8 Table 7 1 Raster Engine Video Mode Output Examples 7 2 Table 7 2 Byte Oriented Frame Buffer Organization 7 5 Table 7 3 Output Pixel Transfer Modes 7 13 Table 7 4 Grayscale Lookup Table GrySclLUT 7 17 Table 7 5 Grayscale Timing Diagram 7 18 Tabl...

Page 19: ...Memory Layout for Destination Image 8 12 Table 8 19 24 BPP Memory Layout for Source Image 8 12 Table 8 20 24 BPP Memory Layout for Destination Image 8 13 Table 8 21 Words Needed for Six 24 Bit Pixels 8 19 Table 8 22 Graphics Accelerator Registers 8 22 Table 8 23 Pixel Mode Encoding 8 30 Table 9 1 FIFO RAM Address Map 9 3 Table 9 2 RXCtl MA and RXCtl IAHA 0 Relationships 9 10 Table 9 3 Ethernet Reg...

Page 20: ...Table 13 6 Sync Memory CAS 13 7 Table 13 7 Sync Memory RAS Burst Type and Write Burst Length 13 7 Table 13 8 Burst Length 13 7 Table 13 9 Chip Select Decoding 13 9 Table 13 10 Memory Addressing Example 13 11 Table 13 11 EP93xx SDRAM Address Ranges 16 Bit Wide Data Systems 13 12 Table 13 12 Address Bits Used for Chip Select 13 17 Table 13 13 Synchronous Memory Controller Registers 13 17 Table 13 14...

Page 21: ... Interaction Between RSIZE and CM Bits 22 11 Table 23 1 SSP Register Memory Map Description 23 13 Table 24 1 Static Programming Steps 24 2 Table 24 2 Dynamic Programming Steps 24 3 Table 24 3 PWM Registers Map 24 3 Table 25 1 Switch Definitions and Logical Safeguards to Prevent Physical Damage 25 3 Table 25 2 Touch Screen Switch Register Configurations 25 7 Table 25 3 External Signal Functions 25 ...

Page 22: ...anges UM1 September 14 2007 This is the Initial Release of the EP93xx User s Guide This manual covers all products in the EP93xx product family This manual is based on the content of previous User s Guides for each of the individual products in the EP93xx family New content has been added formatting improved and all known documentation errors fixed Please discard previous User s Guides and rely on...

Page 23: ...the maximum core frequency and the maximum high speed bus frequency as well as number of package balls and package type for the EP93xx processors Table P 2 shows chapter numbers and function and which EP93xx processors include the function or not Table P 1 Frequency Package Applicable EP93xx Processor EP9301 EP9302 EP9307 EP9312 EP9315 Maximum Core Frequency MHz 166 200 200 200 200 Maximum High Sp...

Page 24: ...als and HDLC X X X X X 15 UART2 with IrDA X X X X X 16 UART3 with HDLC X X X 17 IrDA X X X X X 18 Timers 4 4 4 4 4 19 Watchdog Timer X X X X X 20 Real Time Clock with Software Trim X X X X X 21 I2 S Controller 3 3 3 3 3 22 AC 97 Controller 1 1 1 1 1 23 Synchronous Serial Port 1 1 1 1 1 24 Pulse Width Modulators 2 2 1 2 2 25 Analog Touch Screen Interface ADC 5 ADC 5 ADC 8 Wire TS 8 Wire TS 8 Wire T...

Page 25: ...rd document number ARM QRC 0001D ARM Limited 5 The MAC engine is compliant with the requirements of ISO IEC 8802 3 1993 Sections 3 and 4 6 OpenHCI Open Host Controller interface Specification for USB Release 1 0a Compaq Microsoft National Semiconductor 7 ARM Co processor Quick Reference Card document number ARM QRC 0001D ARM Limited 8 Information Technology AT Attachment with Packet Interface 5 AT...

Page 26: ...ster description is shown below This description is used for the following examples A specific bit may be specified in one of three ways 1 Register name bit number for example SysCfg 29 2 Register name bit field bit number for example SysCfg REV 1 3 Register name bit field bit name for example SysCfg SBOOT Hexidecimal numbers are referred to as 0x0000_0000 Binary numbers are referred to as 0000_00...

Page 27: ...and CSn6 respectively These are used to define the external bus width for the boot code boot LASDO Latched version of ASDO pin Used to select synchronous versus asynchronous boot device LEEDA Latched version of EEDAT pin LEECLK Define Internal or external boot 1 Internal 0 External LCSn1 LCSn2 Define Watchdog startup action 0 0 Watchdog disabled Reset duration disabled 0 1 Watchdog disabled Reset ...

Page 29: ...f high volume applications Furthermore by enabling or disabling the EP93xx processor s peripherals and their interfaces designers can throttle power consumption and reduce development costs and accelerate time to market by creating a single platform that can be easily modified to deliver a variety of differentiated end products 1 2 EP93xx Features Maximum clock rates plus package types and number ...

Page 30: ...Touch Screen ADC GPIO PC Card EP9301 X X 2 2 5 ADC 37 EP9302 X X X 2 2 5 ADC 37 EP9307 X X X X X 3 3 8 Wire 12 ADC 48 EP9312 X X X X 1 3 3 8 Wire 12 ADC 47 EP9315 X X X X X 1 3 3 8 Wire 12 ADC 55 X 5 Channel ADC 2 PWM Enhanced GPIO 2 wire 2 LED I2 S SPI AC 97 RTC with SW Trim Watchdog Timer 4 Timers System Control 2 PLLs UART1 with HDLC SDRAM SRAM FLASH ROM 12 Channel DMA 1 10 100 Ethernet MAC JTA...

Page 31: ...KB Memory Management Unit AHB APB Bridge Vectored Inerrupts High Speed Bus AHB Peripheral Bus APB MaverickCrunchTM Coprocessor 8 Wire Touchscreen ADC 8x8 Matrix Keypad 1 PWM Enhanced GPIO EEPROM 2 LED I2 S SPI AC 97 RTC with SW Trim Watchdog Timer 4 Timers System Control 2 PLLs UART1 with HDLC 18 bit Raster LCD plus CCITT656 Video SDRAM SRAM FLASH ROM 12 Channel DMA 1 10 100 Ethernet MAC JTAG 3 US...

Page 32: ...C MaverickCrunchTM Coprocessor ARM920T I Cache 16 KB D Cache 16 KB Memory Management Unit AHB APB Bridge Vectored Inerrupts High Speed Bus AHB Peripheral Bus APB 8 Wire Touchscreen ADC 8x8 Matrix Keypad 2 PWMs Enhanced GPIO 2 wire 2 LED I2 S SPI AC 97 RTC with SW Trim Watchdog Timer 4 Timers System Control 2 PLLs UART1 with HDLC 18 bit Raster LCD plus CCITT656 Video SDRAM SRAM FLASH ROM PCMCIA 12 ...

Page 33: ...g MaverickKey IDs for Digital Rights Management or Design IP Security 32 bit unique ID 128 bit random ID Integrated Peripherals and Interfaces EIDE up to 2 devices in EP9312 and 9315 only 1 10 100 Mbps Ethernet MAC Two port USB 2 0 Full Speed host OHCI in EP9301 and 9302 only Three port USB 2 0 Full Speed host OHCI in EP9307 9312 and 9315 only IrDA controller slow and fast mode Two UARTs 16550 Typ...

Page 34: ...ly 32 bit SDRAM interface up to 4 banks in EP9307 9312 and 9315 only 16 8 bit SRAM Flash ROM interface in EP9301 and 9302 only 32 16 8 bit SRAM Flash ROM interface in EP9307 9312 and 9315 only Serial Flash interface Internal Peripherals Real Time clock with software trim 12 DMA channels for data transfer to maximize system performance Boot ROM Dual PLLs Watchdog timer Two general purpose 16 bit ti...

Page 35: ...ts Linux Windows CE and many other embedded operating systems The ARM920T s 32 bit microcontroller architecture with a five stage pipeline delivers impressive performance at very low power The included 16 KByte instruction cache and 16 KByte data cache provide zero cycle latency to the current program and data or can be locked to provide guaranteed no latency access to critical instructions and da...

Page 36: ...r DRM Digital Rights Management and other authentication mechanisms MaverickKey uses a specific 32 bit ID and a 128 bit random ID that are programmed into the EP93xx processors through the use of laser probing technology These IDs can then be used to match secure copyrighted content with the ID of the target device that the EP93xx processor is powering and then deliver the copyrighted information ...

Page 37: ... the Boot ROM 1 4 8 Abundant General Purpose I Os Build Flexible Systems The EP93xx processors include both enhanced and standard general purpose I O pins GPIOs The enhanced GPIOs may individually be configured as inputs outputs or interrupt enabled inputs Nineteen enhanced GPIOs are in EP9301 and 9302 processors 18 are in the EP9307 processor and 16 are in EP9312 processor and 24 are in the EP931...

Page 38: ...y be disabled and the switch matrix and ADC controlled directly for general ADC usage if desired 1 4 11 Raster Analog LCD Controller The EP9307 EP9312 and EP9315 processors include a raster LCD controller that features fully programmable video interface timing for either non interlaced or dual scan color and grayscale flat panel displays Resolutions up to 1024x768 pixels are supported from a unifi...

Page 39: ...ecode execute data memory access and write stages 2 2 1 Features Key features include ARM V4T 32 bit and Thumb 16 bit compressed instruction sets 32 bit Advanced Micro Controller Bus Architecture AMBA 16 kbyte Instruction Cache with lockdown 16 kbyte Data Cache programmable write through or write back with lockdown Write Buffer MMU for Microsoft Windows CE and Linux operating systems Translation L...

Page 40: ...e DMA controller and memory modules AMBA includes a AHB APB bridge to the lower speed APB Advanced Peripheral Bus The APB bus connects to lower speed peripheral devices such as UARTs and GPIOs The MMU provides memory address translation for all memory and peripherals designed to remap memory devices and peripheral address locations Sections large small and tiny pages are programmable to map memory...

Page 41: ...at software will function identically across different implementations For memory access instructions the base register used for the access will be restored by the ARM Core in the event of an Abort exception The base register will be restored to the value contained in it immediately before execution of the instruction The ARM9TDMI core memory interface includes a separate instruction and data inte...

Page 42: ... found in the TLB miss the ARM Core will go to external memory and look for the TTB in system memory The internal translation table walks hardware steps through the page table setup in external memory for the appropriate physical address When the physical address is acquired the TLB is updated When the address is found in the TLB system performance will increase since additional cycles to access m...

Page 43: ...14 in CP15 register 1 On a cache miss instruction or data not in the respective cache an 8 word line is fetched from memory and loaded into the cache Independent cache lock down with granularity of 1 64th of total cache size or 256 bytes for both instructions and data Lock down of the cache will prevent an eight word cache line fill into that region of the cache For compatibility with Windows CE a...

Page 44: ... relationship between the ARM co processor instructions and MaverickCrunch co processor is also explained in Chapter 3 The ARM co processor instruction set includes LDC Load co processor from memory STC Store co processor register from memory MRC Move to ARM register from co processor register MCR Move to co processor register from ARM register The ARM co processor has sixteen C0 through C15 64 bi...

Page 45: ...C1 VIC2 DMA LCD Raster registers USB host IDE Ethernet MAC and the bridge to the APB interface The AHB APB Bridge transparently converts the AHB accesses into the slower speed APB accesses All of the control registers for the APB peripherals are programmed using the AHB APB bridge interface The main AHB data and address lines are configured using a multiplexed bus This removes the need for three s...

Page 46: ...by driving the address and control signals These signals provide information on the address direction and width of the transfer as well as indicating whether the transfer is part of a burst Two different forms of burst transfers are allowed Incrementing bursts which do not wrap at address boundaries Wrapping bursts which wrap at particular address boundaries SDRAM Controller Static Memory E B I GP...

Page 47: ...ly decoded so aliasing may occur Addresses and memory ranges listed as Reserved should not be accessed access behavior to these regions is not defined Access to non existent registers or memory may result in a bus error Any access to the APB control register space will complete normally as these devices have no means of signaling an error Access to non existent AHB or APB registers may result in a...

Page 48: ... blocking important interrupt service routines These masters are thereby prevented from accessing the bus that is their bus requests are masked until the IRQ FIQ is removed by the Interrupt Service Routine After the IRQ FIQ is removed their bus requests will again be recognized The default is to program the arbiter so that it does not degrant any of these masters In normal operation when the ARM92...

Page 49: ...ecoding optimization the AHB peripheral registers are aliased throughout each peripherals register bank Do not attempt to access an unspecified register within the bank 2 3 1 AHB Slave An AHB Slave responds to transfers initiated by bus masters The slave uses signals from the decoder to determine when it should respond to a bus transfer All other signals required for the transfer such as the addre...

Page 50: ...nues as normal but no peripherals are selected The APB bridge acts as the only master on the APB The APB memory map is shown in Table 2 3 Table 2 3 APB Peripheral Address Range Address Range Register Width Peripheral Type Peripheral 0x8095_0000 0x9000_FFFF Reserved 0x8094_0000 0x8094_FFFF 16 APB Watchdog Timer 0x8093_0000 0x8093_FFFF 32 APB Syscon 0x8092_0000 0x8092_FFFF 32 APB Real time clock 0x8...

Page 51: ...M instructions state before taking an exception The return instruction will restore the ARM Core to the Thumb state Most tasks are executed out of User mode The ARM920T Core s operating modes are shown in Table 2 4 Table 2 5 illustrates the use of all registers for the ARM920T Core s operating modes Each will bank or store a specific number of registers Banked register information is not shared be...

Page 52: ...ion Summary Privileged Modes Exception Modes User System Supervisor Abort Undefined IRQ FIQ r0 r0 r0 r0 r0 r0 r0 Thumb state low registers r1 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r2 r3 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8 r8_fiq Thumb state high registers r9 r9 r9 r9 r9 r9 r9_fiq r10 r10 r10 r10 r10 r10 r10_fiq r11 r...

Page 53: ...TB 3 Domain Access Control Read Write This register specifies permissions for each of the 16 domains Read Write Instructions are MRC p15 0 Rd c3 c0 0 MCR p15 0 Rd c3 c0 0 4 Reserved Do not access Unpredictable behavior may result 5 Fault Status Read Write This register indicates the type of fault and the domain of the most recent data abort Read Write Instructions are MRC p15 0 Rd c5 c0 0 read dat...

Page 54: ...Global Memory Map for the Two Boot Modes Address Range Sync Memory Boot Async Memory Boot ASD0 Pin 1 ASD0 Pin 0 0xF000_0000 0xFFFF_FFFF Async memory nCS0 Sync memory nSDCE3 0xE000_0000 0xEFFF_FFFF Sync memory nSDCE2 Sync memory nSDCE2 0xD000_0000 0xDFFF_FFFF Sync memory nSDCE1 Sync memory nSDCE1 0xC000_0000 0xCFFF_FFFF Sync memory nSDCE0 Sync memory nSDCE0 0x9000_0000 0xBFFF_FFFF Not Used Not Used...

Page 55: ...may be controlled with a software lock Each peripheral with software lock capability has its own software lock register Within a register definition a reserved bit indicated by the name RSVD means the bit is not accessible Software should mask the RSVD bits when doing bit reads RSVD bits will ignore writes that is writing a zero or a one has no affect Register bits identified as NC are functionall...

Page 56: ..._0018 MIISts MAC MII Status Register N 0x8001_0020 SelfCtl MAC Self Control Register N 0x8001_0024 IntEn MAC Interrupt Enable Register N 0x8001_0028 IntStsP MAC Interrupt Status Preserve Register N 0x8001_002C IntStsC MAC Interrupt Status Clear Register N 0x8001_0030 0x8001_0034 Reserved 0x8001_0038 DiagAd MAC Diagnostic Address Register N 0x8001_003C DiagDa MAC Diagnostic Data Register N 0x8001_0...

Page 57: ...ueue Current Length Register N 0x8001_00C8 TXStsQCurAdd MAC Transmit Status Queue Current Address Register N 0x8001_00D0 RXBufThrshld MAC Receive Buffer Threshold Register N 0x8001_00D4 TXBufThrshld MAC Transmit Buffer Threshold Register N 0x8001_00D8 RXStsThrshld MAC Receive Status Threshold Register N 0x8001_00DC TXStsThrshld MAC Transmit Status Threshold Register N 0x8001_00E0 RXDThrshld MAC Re...

Page 58: ...horizontal line clocks Y 0x8003_0014 HSyncStrtStop Horizontal sync pulse setup Y 0x8003_0018 HActiveStrtStop Horizontal blanking setup Y 0x8003_001C HClkStrtStop Horizontal clock active frame Y 0x8003_0020 Brightness PWM brightness control N 0x8003_0024 VideoAttribs Video state machine parameters Y 0x8003_0028 VidScrnPage Starting address of video screen N 0x8003_002C VidScrnHPage Starting address...

Page 59: ...kRateCtrl Cursor Blink rate control Register N 0x8003_0228 VBlankStrtStop Vertical Blank signal Start Stop Register N 0x8003_022C HBlankStrtStop Horizontal Blank signal Start Stop Register N 0x8003_0230 EOLOffset End Of Line Offset value N 0x8003_0234 FIFOLevel FIFO refill level Register N 0x8003_0280 0x8003_02FC GrySclLUTG Grayscale Look Up Table N 0x8003_0300 0x8003_037C GrySclLUTB Grayscale Loo...

Page 60: ... Boot ROM Memory Locations 0x8009_0000 Boot ROM Start N 0x8009_3FFF Boot ROM End N 0x800A_xxxx IDE IDE Control Registers 0x800A_0000 IDECtrl IDE Control Register N 0x800A_0004 IDECfg IDE Configuration Register N 0x800A_0008 IDEMDMAOp IDE MDMA Operation Register N 0x800A_000C IDEUDMAOp IDE UDMA Operation Register N 0x800A_0010 IDEDataOut IDE PIO Data Output Register N 0x800A_0014 IDEDataIn IDE PIO ...

Page 61: ...address 10 Register N 0x800B_012C VIC1VectAddr11 Vector address 11 Register N 0x800B_0130 VIC1VectAddr12 Vector address 12 Register N 0x800B_0134 VIC1VectAddr13 Vector address 13 Register N 0x800B_0138 VIC1VectAddr14 Vector address 14 Register N 0x800B_013C VIC1VectAddr15 Vector address 15 Register N 0x800B_0200 VIC1VectCntl0 Vector control 0 Register N 0x800B_0204 VIC1VectCntl1 Vector control 1 R...

Page 62: ...egister N 0x800C_0110 VIC2VectAddr4 Vector address 4 Register N 0x800C_0114 VIC2VectAddr5 Vector address 5 Register N 0x800C_0118 VIC2VectAddr6 Vector address 6 Register N 0x800C_011C VIC2VectAddr7 Vector address 7 Register N 0x800C_0120 VIC2VectAddr8 Vector address 8 Register N 0x800C_0124 VIC2VectAddr9 Vector address 9 Register N 0x800C_0128 VIC2VectAddr10 Vector address 10 Register N 0x800C_012...

Page 63: ...002C Timer2Clear Clears an interrupt generated by the timer N 0x8081_0060 0x8081_0064 Reserved 0x8081_0080 Timer3Load Contains the initial value of the timer N 0x8081_0084 Timer3Value Gives the current value of the timer N 0x8081_0088 Timer3Control Provides enable disable and mode configurations for the timer N 0x8081_008C Timer3Clear Clears an interrupt generated by the timer N 0x8082_xxxx I2S I2...

Page 64: ...O Port A Data Register N 0x8084_0004 PBDR GPIO Port B Data Register N 0x8084_0008 PCDR GPIO Port C Data Register N 0x8084_000C PDDR GPIO Port D Data Register N 0x8084_0010 PADDR GPIO Port A Data Direction Register N 0x8084_0014 PBDDR GPIO Port B Data Direction Register N 0x8084_0018 PCDDR GPIO Port C Data Direction Register N 0x8084_001C PDDDR GPIO Port D Data Direction Register N 0x8084_0020 PEDR...

Page 65: ...B0 GPIOBIntType2 Register controlling polarity high low or rising falling of interrupt generated by Port B N 0x8084_00B4 GPIOBEOI GPIO Port B End Of Interrupt Register N 0x8084_00B8 GPIOBIntEn Controlling the generation of interrupts by the pins of Port B N 0x8084_00BC IntStsB GPIO Interrupt Status Register Contains status of Port B interrupts after masking N 0x8084_00C0 RawIntStsB Raw Interrupt S...

Page 66: ...080 AC97S1Data Data received transmitted on SLOT1 N 0x8088_0084 AC97S2Data Data received transmitted on SLOT2 N 0x8088_0088 AC97S12Data Data received transmitted on SLOT12 N 0x8088_008C AC97RGIS Raw Global interrupt status Register N 0x8088_0090 AC97GIS Global interrupt status Register N 0x8088_0094 AC97IM Interrupt mask Register N 0x8088_0098 AC97EOI End Of Interrupt Register N 0x8088_009C AC97GC...

Page 67: ... 0x808C_0020 Reserved 0x808C_0028 UART1DMACtrl UART1 DMA Control Register N 0x808C_0100 UART1ModemCtrl UART1 Modem Control Register N 0x808C_0104 UART1ModemSts UART1 Modem Status Register N 0x808C_0114 0x808C_0208 Reserved 0x808C_020C UART1HDLCCtrl UART1 HDLC Control Register N 0x808C_0210 UART1HDLCAddMtchVal UART1 HDLC Address Match Value N 0x808C_0214 UART1HDLCAddMask UART1 HDLC Address Mask N 0...

Page 68: ...3HDLCAddMask UART3 HDLC Address Mask N 0x808E_0218 UART3HDLCRXInfoBuf UART3 HDLC Receive Information Buffer N 0x808E_021C UART3HDLCSts UART3 HDLC Status Register N 0x808F_xxxx KEY Key Matrix Control Registers 0x808F_0000 KeyScanInit Key Matrix Scan Initialize N 0x808F_0004 KeyDiagnostic Key Matrix Diagnostic N 0x808F_0008 KeyRegister Key Matrix Key Register N 0x8090_xxxx TOUCH Touchscreen Control ...

Page 69: ... mode N 0x8093_0018 TEOI Write to clear Watchdog interrupt N 0x8093_001C STFClr Write to clear Nbflg rstflg pfflg and cldflg N 0x8093_0020 ClkSet1 Clock speed control 1 N 0x8093_0024 ClkSet2 Clock speed control 2 N 0x8093_0040 ScratchReg0 Scratch Register 0 N 0x8093_0044 ScratchReg1 Scratch Register 1 N 0x8093_0050 APBWait APB wait N 0x8093_0054 BusMstrArb Bus Master Arbitration N 0x8093_0058 Boot...

Page 70: ...right 2007 Cirrus Logic ARM920T Core and Advanced High Speed Bus AHB EP93xx User s Guide 22 2 0x8095_0000 0x8FFF_FFFF Reserved Table 2 8 Internal Register Map Continued Address Register Name Register Description SW Lock ...

Page 71: ...y interface and instruction stream All MaverickCrunch operations are simply ARM920T co processor instructions The co processor handles all internal inter instruction dependencies by using internal data forwarding and inserting wait states 3 1 1 Features Key features include IEEE 754 single and double precision floating point 32 64 bit integer Add multiply compare Integer Multiply Accumulate MAC 32...

Page 72: ...integers the co processor provides multiply accumulate MAC multiply subtract MSB Any of the four data formats may be converted to another of the formats All four data types may be loaded directly from and stored directly to memory via the ARM920T co processor interface They may also be moved to or from ARM920T registers The MaverickCrunch co processor also provides a 72 bit extended precision inte...

Page 73: ...ssuming no inter instruction dependencies causing pipeline stalls arithmetic instructions can produce a new result every two ARM920T clocks which is a maximum throughput of one data path instruction per eight ARM920T clocks The only exception is 64 bit multiplies CFMULD or CFMUL64 which require six extra ARM920T clocks to produce their result which is maximum throughput of eight ARM920T clocks per...

Page 74: ...from floating point to integer format Instructions that may saturate their results are CFADD32 and CFADD64 CFSUB32 and CFSUB64 CFMUL32 and CFMUL64 CFMAC32 and CFMSC32 CFCVTS32 and CFCVTD32 CFTRUNCS32 and CFTRUNCD32 This behavior however can be altered by setting the UI bit and the ISAT bit in the DSPSC With the UI bit clear the default 32 bit and 64 bit integer operations are treated as signed wit...

Page 75: ...t do not write their result to an accumulator Enabling saturation also modifies the representation of data stored in the accumulator The three supported bit formats and their maximum and minimum saturation values are shown in Table 3 2 The bit format x yy represents x binary bits before the decimal point and yy fraction bits after the decimal point as for example when the bit format 2 62 has two b...

Page 76: ...integer CFCMP64 64 bit integer CFCMPS single floating point CFCMPD double floating point The DSPSC register bit UINT affects the operation of integer comparisons If clear integers are treated as signed values and if set they are treated as unsigned DSPSC UINT has no effect on floating point comparisons All compare operations update both the FCC 1 0 bits in the DSPSC register and an ARM register Th...

Page 77: ...ns using the ARM CMP instruction Hence when examining the result of Crunch comparisons the condition codes field of ARM instructions should be interpreted differently as shown in Table 3 4 The same six condition codes should be used whether the comparison operands were signed integers unsigned integers or floating point No other condition codes are meaningful Table 3 3 Comparison Relationships and...

Page 78: ...ess mov r1 0xaa SW lock key str r1 r0 0xc0 unlock by writing key to SysSWLock register ldr r1 r0 0x80 Turn on CPENA bit in DEVCFG register to orr r1 r1 0x00800000 enable MaverickCrunch co processor str r1 r0 0x80 3 2 1 2 C Code int num 0 for num 0 num 10 num num num 5 3 2 1 3 Accessing MaverickCrunch with ARM Co Processor Instructions ldc p5 c0 r0 0x0 data section preloaded with 0x0 num ldc p5 c1 ...

Page 79: ...umber of samples for which the filter should be applied filter is the FIR filter to be applied and m is the number of taps in the FIR filter The data array must be n m 1 samples in length and n samples will be produced 3 2 2 1 C Code void ComputeFIR float data int n float filter int m int i j float sum for i 0 i n i sum 0 for j 0 j m j sum data i j filter j data i sum 3 2 2 2 MaverickCrunch Assemb...

Page 80: ...ts including status bits are both readable and writable This register should generally be written only using a read modify write sequence Bit Descriptions RSVD Reserved Unknown During Read INST Exception Instruction Whenever an unmasked exception occurs these 32 bits are loaded with the instruction that caused the exception Hence this contains the instruction that caused the most recent unmasked e...

Page 81: ...0 Signed integers 1 Unsigned integers INT MaverickCrunch Interrupt This bit indicates whether an interrupt has occurred This bit is identical to the external interrupt signal 0 No interrupt signaled 1 Interrupt signaled AEXC Asynchronous Exception Enable This bit determines whether exceptions generated by the co processor are signaled synchronously or asynchronously to the ARM920T Synchronous exce...

Page 82: ... Enable This bit determines whether data path writeback results are forwarded to the data path operand fetch stage and to the STC MRC execute stage When pipeline interlocks occur due to dependencies of data path STC and MRC instruction source operands on data path results setting this bit will improve instruction throughput 0 Forwarding not enabled 1 Forwarding enabled Invalid 0 No invalid operati...

Page 83: ...f whether or not software trapping for inexact exceptions is enabled Writing a 0 to this position clears the status bit 0 No inexact exception detected 1 Inexact exception detected UF Underflow Set when an IEEE 754 underflow exception occurs regardless of whether or not software trapping for underflow exceptions is enabled Writing a 0 to this position clears the status bit 0 No underflow exception...

Page 84: ...bove instructions and variants of these instructions are detailed below CDP Co Processor Data Processing Instruction Format LDC Load Co Processor Instruction Format STC Store Co Processor Instruction Format MCR Move to Co Processor from ARM Register Instruction Format MRC Move to ARM Register from Co Processor Instruction Format 31 28 27 24 23 20 19 16 15 12 11 8 7 5 4 3 0 cond 1110 opcode1 CRn CR...

Page 85: ...t is added to a base register U 1 or subtracted from a base register U 0 This bit is ignored by the MaverickCrunch co processor N Specifies the width of a data type involved in a move operation The MaverickCrunch Table 3 5 Condition Code Definitions Cond 31 28 Mnemonic Extension Meaning Status Flag State 0000 EQ Equal Z set 0001 NE Not Equal Z clear 0010 CS HS Carry Set Unsigned Higher or Same C s...

Page 86: ...opcode2 opcode1 and cp_num for all of the MaverickCrunch instructions Table 3 6 LDC STC Opcode Map cp num 3 0 Opcode Bits 22 and 20 00 01 10 11 0100 0101 cfstrs cfstr32 cfldrs cfldr32 cfstrd cfstr64 cfldrd cfldr64 Table 3 7 CDP Opcode Map op code 1 1 0 cp num 3 0 opcode2 2 0 000 001 010 011 100 101 110 111 00 0100 cfcpys cfcpyd cfcvtds cfcvtsd cfcvt32s cfcvt32d cfcvt64s cfcvt64d 0101 cfsh32 0110 c...

Page 87: ...er of this section describes in detail each of the individual MaverickCrunch instructions The fields in the opcode for each MaverickCrunch instruction are shown When specific bit values are required for the instruction they are shown as either 1 or 0 Any field whose value may vary such as a register index is named as in the ARM programming manuals and its function described below Table 3 8 MCR Opc...

Page 88: ... in CRd at address in Rn Moves to co processor MCR cfmvsr CRn Rd Move single from Rd to CRn 63 32 cfmvdlr CRn Rd Move lower half of double from Rd to CRn 31 0 cfmvdhr CRn Rd Move upper half of double from Rd to CRn 63 32 cfmv64lr CRn Rd Move lower half of 64 bit integer from Rd to CRn 31 0 sign extend bit 31 through bits 63 31 cfmv64hr CRn Rd Move upper half of 64 bit integer from Rd to CRn 63 32 ...

Page 89: ... Convert a 32 bit integer in CRn to a single in CRd cfcvt32d CRd CRn Convert a 32 bit integer in CRn to a double in CRd cfcvt64s CRd CRn Convert a 64 bit integer in CRn to a single in CRd cfcvt64d CRd CRn Convert a 64 bit integer in CRn to a double in CRd cfcvts32 CRd CRn Convert a single in CRn to a 32 bit integer in CRd cfcvtd32 CRd CRn Convert a double in CRn to a 32 bit integer in CRd cftruncs...

Page 90: ... CRn CRm CRd gets the product of CRn and CRm Floating point arithmetic double precision CDP cfabsd CRd CRn CRd gets absolute value of CRn cfnegd CRd CRn CRd gets negation of CRn cfaddd CRd CRn CRm CRd gets sum of CRn and CRm cfsubd CRd CRn CRm CRd gets CRn minus CRm cfmuld CRd CRn CRm CRd gets the product of CRn and CRm 32 bit integer arithmetic CDP cfabs32 CRd CRn CRd gets absolute value of CRn c...

Page 91: ...CRn and CRm cfmsub32 CRa CRd CRn CRm Accumulator CRa gets CRd minus the product of CRn and CRm cfmadda32 CRa CRd CRn CRm Accumulator CRa gets sum of accumulator CRd and the product of CRn and CRm cfmsuba32 CRa CRd CRn CRm Accumulator CRa gets accumulator CRd minus the product of CRn and CRm 31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 0 cond 1 1 0 P U N W 1 Rn CRd 0 1 0 0 8_bit_word_offset Table ...

Page 92: ...er Store Floating Point Values to Memory Description Stores a single or double precision floating point value from a MaverickCrunch register into memory 31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 0 cond 1 1 0 P U N W 1 Rn CRd 0 1 0 1 8_bit_word_offset Table 3 12 Mnemonic Codes for Loading Integer Value from Memory Mnemonic Addressing Mode N CFLDR32 cond CRd Rn offset Immediate pre indexed 0 CFL...

Page 93: ...monic Codes for Storing Floating Point Values to Memory Mnemonic Addressing Mode N CFSTRS cond CRd Rn offset Immediate pre indexed 0 CFSTRS cond CRd Rn offset Immediate post indexed 0 CFSTRD cond CRd Rn offset Immediate pre indexed 1 CFSTRD cond CRd Rn offset Immediate post indexed 1 31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 0 cond 1 1 0 P U N W 0 Rn CRd 0 1 0 1 8_bit_word_offset Table 3 14 Mn...

Page 94: ...alf of a MaverickCrunch register to an ARM register Mnemonic CFMVRS cond Rd CRn Bit Definitions Rd Destination ARM register CRn Source register Move Lower Half Double Precision Float from ARM to MaverickCrunch Description Moves the lower half of a double precision floating point value from an ARM register into the lower half of a MaverickCrunch register Mnemonic CFMVDLR cond CRn Rd Bit Definitions...

Page 95: ...M register into the upper half of a MaverickCrunch register Mnemonic CFMVDHR cond CRn Rd Bit Definitions CRn Destination register Rd Source ARM register Move Upper Half Double Precision Float from MaverickCrunch to ARM Description Moves the upper half of a double precision floating point value stored in a MaverickCrunch register into an ARM register Mnemonic CFMVRDH cond Rd CRn Bit Definitions Rd ...

Page 96: ...a MaverickCrunch register into an ARM register Mnemonic CFMVR64L cond Rd CRn Bit Definitions Rd Destination ARM register CRn Source register Move Upper Half 64 bit Integer from ARM to MaverickCrunch Description Moves the upper half of a 64 bit integer from an ARM register into the upper half of a MaverickCrunch register Mnemonic CFMV64HR cond CRn Rd Bit Definitions CRn Destination register Rd Sour...

Page 97: ...nch register to the lowest 32 bits of an accumulator 31 0 Mnemonic CFMVAL32 cond CRd CRn Bit Definitions CRd Destination accumulator CRn Source register Move Lower Accumulator to MaverickCrunch Register Description Moves the lowest 32 bits of an accumulator 31 0 to the low 32 bits of a MaverickCrunch register Mnemonic CFMV32AL cond CRd CRn Bit Definitions CRd Destination register CRn Source accumu...

Page 98: ...of a MaverickCrunch register Mnemonic CFMV32AM cond CRd CRn Bit Definitions CRd Destination register CRn Source accumulator Move MaverickCrunch Register to High Accumulator Description Moves the lowest 8 bits 7 0 of a MaverickCrunch register to the highest 8 bits of an accumulator 71 64 Mnemonic CFMVAH32 cond CRd CRn Bit Definitions CRd Destination accumulator CRn Source register 31 28 27 24 23 22...

Page 99: ...to the low 32 bits of a MaverickCrunch register Mnemonic CFMV32A cond CRd CRn Bit Definitions CRd Destination register CRn Source accumulator Move 32 bit Integer to Accumulator Description Moves a 32 bit value from a MaverickCrunch register to an accumulator and sign extend to 72 bits Mnemonic CFMVA32 cond CRd CRn Bit Definitions CRd Destination accumulator CRn Source register 31 28 27 24 23 22 21...

Page 100: ...ts Mnemonic CFMVA64 cond CRd CRn Bit Definitions CRd Destination accumulator CRn Source register Move from MaverickCrunch Register to Control Status Register Description Moves a 64 bit value from a MaverickCrunch register to the MaverickCrunch Status Control register DSPSC All DSPSC bits are writable CRn is ignored Mnemonic CFMVSC32 cond CRd CRn Bit Definitions CRd Source register 31 28 27 24 23 2...

Page 101: ...precision floating point value from one register to another Mnemonic CFCPYS cond CRd CRn Bit Definitions CRd Destination register CRn Source register Copy Double Precision Floating Point Description Copies a double precision floating point value from one register to another Mnemonic CFCPYD cond CRd CRn Bit Definitions CRd Destination register CRn Source register 31 28 27 24 23 22 21 20 19 16 15 12...

Page 102: ...oating point value to a single precision floating point value Mnemonic CFCVTDS cond CRd CRn Bit Definitions CRd Destination register CRn Source register Convert 32 bit Integer to Single Precision Floating Point Description Converts a 32 bit integer to a single precision floating point value Mnemonic CFCVT32S cond CRd CRn Bit Definitions CRd Destination register CRn Source register 31 28 27 24 23 2...

Page 103: ... floating point value Mnemonic CFCVT64S cond CRd CRn Bit Definitions CRd Destination register CRn Source register Convert 64 bit Integer to Double Precision Floating Point Description Converts a 64 bit integer to a double precision floating point value Mnemonic CFCVT64D cond CRd CRn Bit Definitions CRd Destination register CRn Source register 31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 5 4 3 0 cond...

Page 104: ... Floating Point to 32 bit Integer Description Truncates a single precision floating point number to a 32 bit integer Mnemonic CFTRUNCS32 cond CRd CRn Bit Definitions CRd Destination register CRn Source register Truncate Double Precision Floating Point to 32 bit Integer Description Truncates a double precision floating point number to a 32 bit integer Mnemonic CFTRUNCD32 cond CRd CRn 31 28 27 24 23...

Page 105: ...Rd Bit Definitions CRm Destination register CRn Source register Rd Shift count register in ARM Shift 64 bit Integer Definition Shifts a 64 bit integer left or right The shift count is a two s complement integer stored in an ARM register the count is positive for left shifts and negative for right shifts This instruction may also be used to copy a 64 bit integer from one register to another using a...

Page 106: ...struction may also be used to copy a 64 bit integer from one register to another by using a shift value of 0 Mnemonic CFSH64 cond CRd CRn Shift 6 0 Bit Definitions CRd Destination register CRn Source register Shift 6 0 Shift count 3 5 6 Compare Instructions Compare Single Precision Floating Point Definition Compares two single precision floating point numbers and stores an integer representing the...

Page 107: ...atus register CPSR Mnemonic CFCMPD cond Rd CRn CRm Bit Definitions CRn First source register CRm Second source register Rd Destination ARM register If Rd 15 destination is ARM N C Z and V flags Compare 32 bit Integers Definition Compares two 32 bit integers and stores an integer representing the result in the ARM920T register the highest four bits of the integer result match the N Z C and V bits r...

Page 108: ...ond source register Rd Destination ARM register If Rd 15 destination is ARM N C Z and V flags 3 5 7 Floating Point Arithmetic Instructions Single Precision Floating Point Absolute Value Description Computes the absolute value of a single precision floating point number CRd CRn Mnemonic CFABSS cond CRd CRn Bit Definitions CRd Destination register CRn Source register Double Precision Floating Point ...

Page 109: ...ble precision floating point number Mnemonic CFNEGD cond CRd CRn Bit Definitions CRd Destination register CRn Source register Single Precision Floating Point Add Description Adds two single precision floating point numbers CRd CRn CRm Mnemonic CFADDS cond CRd CRn CRm Bit Definitions CRd Destination register CRn Addend register CRm Addend register 31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 5 4 3 0 ...

Page 110: ...CFSUBS cond CRd CRn CRm Bit Definitions CRd Destination register CRn Minuend register CRm Subtrahend register Double Precision Floating Point Subtract Description Subtracts two double precision floating point numbers Mnemonic CFSUBD cond CRd CRn CRm Bit Definitions CRd Destination register CRn Minuend register CRm Subtrahend register 31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 5 4 3 0 cond 1 1 1 0 ...

Page 111: ...rs Mnemonic CFMULD cond CRd CRn CRm Bit Definitions CRd Destination register CRn Multiplicand register CRm Multiplicand register 3 5 8 Integer Arithmetic Instructions 32 bit Integer Absolute Value Description Computes the absolute value of a 32 bit integer Mnemonic CFABS32 cond CRd CRn Bit Definitions CRd Destination register CRn Source register 31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 5 4 3 0 c...

Page 112: ...e register 64 bit Integer Negate Description Negate a 64 bit integer Mnemonic CFNEG64 cond CRd CRn Bit Definitions CRd Destination register CRn Source register 32 bit Integer Add Description Adds two 32 bit integers 31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 5 4 3 0 cond 1 1 1 0 0 0 1 1 CRn CRd 0 1 0 1 0 0 1 0 CRm 31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 5 4 3 0 cond 1 1 1 0 0 0 1 1 CRn CRd 0 1 ...

Page 113: ...2 bit Integer Subtract Description Subtracts two 32 bit integers Mnemonic CFSUB32 cond CRd CRn CRm Bit Definitions CRd Destination register CRn Minuend register CRm Subtrahend register 64 bit Integer Subtract Description Subtracts two 64 bit integers Mnemonic CFSUB64 cond CRd CRn CRm 31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 5 4 3 0 cond 1 1 1 0 0 0 1 1 CRn CRd 0 1 0 1 1 0 1 0 CRm 31 28 27 24 23 ...

Page 114: ...lies two 64 bit integers Mnemonic CFMUL64 cond CRd CRn CRm Bit Definitions CRd Destination register CRn Multiplicand register CRm Multiplicand register 32 bit Integer Multiply Add Description Multiplies two 32 bit integers and adds the result to another 32 bit integer CRd CRd CRn CRm Mnemonic CFMAC32 cond CRd CRn CRm 31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 5 4 3 0 cond 1 1 1 0 0 0 0 1 CRn CRd 0...

Page 115: ...tiplicand register CRm Multiplicand register 3 5 9 Accumulator Arithmetic Instructions 32 bit Integer Multiply Add Result to Accumulator Description Multiplies two 32 bit integers adds the product to a third 32 bit integer and stores the result in an accumulator CRa CRd CRn CRm Mnemonic CFMADD32 cond CRa CRd CRn CRm Bit Definitions CRa Destination accumulator CRd Addend register CRn Multiplicand r...

Page 116: ...d register CRn Multiplicand register CRm Multiplicand register 32 bit Integer Multiply Add to Accumulator Description Multiplies two 32 bit integers adds the product to an accumulator and stores the result in an accumulator CRa CRd CRn CRm Mnemonic CFMADDA32 cond CRa CRd CRn CRm Bit Definitions CRa Destination accumulator CRd Addend accumulator CRn Multiplicand register CRm Multiplicand register 3...

Page 117: ...it integers subtracts the product from an accumulator and stores the result in an accumulator CRa CRd CRn CRm Mnemonic CFMSUBA32 cond CRa CRd CRn CRm Bit Definitions CRa Destination accumulator CRd Specifies minuend accumulator CRn Multiplicand register CRm Multiplicand register 31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 5 4 3 0 cond 1 1 1 0 0 0 1 1 CRn CRd 0 1 1 0 CRa 0 CRm ...

Page 119: ...ase address base is 0x8009_0000 It will alias on 16 kbyte intervals When internal boot is active the Boot ROM is double decoded and appears at its normal address base and at address 0x0000_0000 At address 0x0000_0000 plus the current offset the Boot ROM can write the BootModeClr bit to remap itself back to 0x8009_0000 plus the current offset Execution then continues with the instruction at the nex...

Page 120: ... 4 1 2 1 Image Header For images copied from the SPI Serial Flash or external FLASH one of the ASCII strings CRUS or SURC must be present as a HeaderID prefixed to an executable image 4 1 2 2 Boot Algorithm The steps in the software boot process are 1 Remap memory 2 Turn the green LED off and the red LED on 3 Disable the Watchdog timer 4 Read the Boot State 5 Set up the Clocks to run from external...

Page 121: ...I in FLASH memory at FLASH Base 0x1000 and verify the HeaderID This is read in for each FLASH Chip select see Figure 4 1 and then follow Steps A and B A Turn on Green LED B Jump to the start of FLASH memory 11 Attempt to read the CRUS or SURC HeaderID in ASCII in memory at 0xC000_0000 and 0xF000_0000 and verify the HeaderID This is read in for SDRAM or SyncFLASH boot see Figure 4 1 and then follow...

Page 122: ...ions Table 4 1 shows configuration settings that are common to all boot modes Set Up Clocks Set Up Memory Download Code Boot Download Start Internal Boot Copy Code Boot Code Copy Read Boot State UART Download SPI Boot Copy Vectors Flash Green Led Boot Flash SDCS 6 or 7 Flash Boot Boot Sync SDCS 0 or 3 Sync Boot See 4 2 3 See 4 2 4 ...

Page 123: ...nd CSn0 The selection of the bus width is determined by latched CSn 7 6 value 8 bit 16 bit 32 bit 32 bit 1 1 0 1 x xx Internal boot from UART1 1 1 0 0 x xx Internal SPI boot if HeaderID is found 1 1 0 0 1 0 0 0 1 1 0 1 1 Internal boot using SYNC boot mode at the chip select where the HeaderID exists The selection of the bus width is determined by latched CSn 7 6 value 16 bit 16 bit 32 bit 32 bit S...

Page 124: ...rom the SPI ROM place the ASCII CRUS or SURC value in the HeaderID at the first location in the ROM The code will be copied from the SPI ROM to the Ethernet buffer at address 0x8001_4000 with a length of 2048 bytes Code execution will start at 0x8001_4000 MAC base 0x4000 The ARM Core will be in SVC mode At this point the user can use the code in the MAC buffer to load the rest of the image from th...

Page 125: ...f commands as shown in Figure 4 2 Figure 4 2 Flow chart of Boot Sequence for 16 bit SDRAM Devices To boot from SDRAM or SyncFLASH put the ASCII CRUS or SURC value in the HeaderID at one of the following locations this location is Base 0x0 0xC000_0000 0xF000_0000 Code execution will start at address Base 0x4 The ARM Core will be in SVC mode Alternatively to boot from SDRAM or SyncFLASH put the ASCI...

Page 126: ...yright 2007 Cirrus Logic Boot ROM EP93xx User s Guide 44 4 3 Run the internal boot code and boot from FLASH 4 Set the PLL back to use the external clock 5 Set up the SDRAM 6 Load the programs to SDRAM 7 Run from SDRAM ...

Page 127: ...TOn external pin for user reset Three key reset externally generated by a Keypad behaves like user reset Watchdog reset internally generated Software reset internally generated During the time that any reset is active the system is halted until it exits the reset state When the device starts with an external PRSTn or RSTOn certain hardware configurations are determined and some system configuratio...

Page 128: ...ed at system wake up The Hardware Configuration controls are defined by a set of device pins that are latched into configuration control bits on the rising edge of the PRSTn or RSTOn pin The different hardware configuration bits define watchdog behavior boot mode internal or external boot synchronicity and external boot width The latched pins are described in Table 5 1 The latched version of these...

Page 129: ...ot fusing Sync boot mode and SDCSn3 The media type must be either SROM or SyncFLASH The selection of the bus width is determined by latched CSn 7 6 value 16 bit 16 bit 32 bit 32 bit 0 1 0 0 0 0 0 0 1 1 0 1 1 External boot using Async boot mode and CSn0 The selection of the bus width is determined by latched CSn 7 6 value 8 bit 16 bit 32 bit 32 bit 1 1 0 1 x xx Internal boot from UART1 1 1 0 0 x xx...

Page 130: ...al or other external clock source The ARM Core is designed so that once it has been configured its CPU speed bus speeds and video clocks may be set to a number of different speeds without affecting the speeds of other clocks in the processor 5 1 5 1 Oscillators and Programmable PLLs The EP93xx has an interface to two external crystal oscillators 32 768 KHz and 14 7456 MHz To generate the required ...

Page 131: ...ser must be aware of the requirements of PLL operation They are PLL1_X1 desired reference clock frequency range is 11 058 MHz and 200 MHz PLL1_X1 output frequency range is 294 MHz and 368 MHz PLL1_X2 desired reference clock frequency after PLL1_X2IPD divider is 12 9 MHz and 200 MHz PLL1_X2 output BEFORE the PS divide must be 290 MHz and 528 MHz The same conditions apply to PLL2 and the ClkSet2 reg...

Page 132: ...bus clock HCLK and the APB bus clock PCLK CPU and Bus Clocks USB and FIR Clocks CPU and Bus Clocks 32 KHz Peripheral Clocks PLL1 PLL2 Clocks Audio Clocks MIR Clock Touch Clock Video Divide 32 KHz Oscillator WATCH_CLK 14 7456 MHz Oscillator PLL1 CFG PLL2 CFG UARTxCLK SSPCLK PWMCLK Timer Clocks FCLK HCLK PCLK USBHost48MHz USBHost12MHz FIR_CLK VCLK SCLK LRCLK MCLK MIR_CLK KEY_CLK TOUCH_CLK ADC_CLK FI...

Page 133: ...0 MHz HCLK 100 MHz and PCLK 50 MHz and FCLK HCLK PCLK Refer to register ClkSet1 on page 5 18 for the detailed configuration information regarding the divider bit fields HCLK Div FCLK Div PLL1 External Clock PCLK Div FCLK HCLK PCLK FCLK Divide 1 2 4 8 16 HCLK Divide 1 2 4 5 6 For 2nd stage dividers PCLK Divide 1 2 4 8 MAX 100 MHz MAX 250 MHz MAX 500 MHz MAX 50 MHz 8 16 32 ...

Page 134: ...re further divided down from MCLK The registers MIRClkDiv on page 5 30 VidClkDiv on page 5 29 and I2SClkDiv on page 5 31 show the details USB uses a 48 MHz clock generated by PLL2 USBDIV in register ClkSet2 on page 5 20 is used to divide the frequency down from the PLL2 output The Key Matrix and Touchscreen Controller clocks are generated from an external 14 7 MHz oscillator A chain of dividers ge...

Page 135: ... to the desired values and enable them The clocks won t actually begin running until the clock sources which feed them are enabled Write the desired values to these registers VidClkDiv on page 5 29 MIRClkDiv on page 5 30 I2SClkDiv on page 5 31 KeyTchClkDiv on page 5 32 6 All peripherals are now running from divided PLL outputs Once the clocks have been configured the frequency of any peripheral cl...

Page 136: ... power states Run mode Normal operation mode Halt ARM Core stops executing instructions Standby Power is on but only SDRAM self refresh and the RTC run Figure 5 4 illustrates the transitions among power states Table 5 4 Peripherals with PCLK Gating Peripheral Peripheral PCLK on with Enable or Register Access PCLK on with Register Access Only PCLK Continuous UART1 x UART2 x UART3 x KEYPAD x IRDA x ...

Page 137: ... into Standby mode However the system will automatically come back to normal operation after new clock settings take effect The amount of time the EP93xx remains in the Standby state depends on whether the PLL is enabled or if the EP93xx is using the external clock If the PLL is enabled the EP93xx will remain in Standby until the PLL is locked If the EP93xx is in PLL bypass mode nBYP1 1 then the E...

Page 138: ...xx comes out of Standby if an interrupt occurs or when an exit from a ClkSet1 write occurs If a write is performed to the ClkSet1 register the EP93xx then enters Standby mode and then automatically comes out of Standby mode and back into the Run state 5 1 6 2 5 HALT RUN mode The transition from the Halt state to the Run state is caused by A falling edge on IRQ interrupt A falling edge on FIQ inter...

Page 139: ...No W 32 Write to clear CLDFLG RSTFLG and WDTFLG 0x8093_0020 ClkSet1 No R W 32 Clock speed control 1 0x8093_0024 ClkSet2 No R W 32 Clock speed control 2 0x8093_0040 ScratchReg0 No R W 32 Scratch register 0 0x8093_0044 ScratchReg1 No R W 32 Scratch register 1 0x8093_0050 APBWait No R W 32 APB wait 0x8093_0054 BusMstrArb No R W 32 Bus Master Arbitration 0x8093_0058 BootModeClr No W 32 Boot Mode Clear...

Page 140: ... Registered PLL1 lock This is a one shot registered signal of the PLL1_LOCK signal It is only cleared on a power on reset when the device enters the Standby state or when PLL1 is powered down PLL2_LOCK PLL2 lock This signal goes high when PLL2 is locked and it is at the correct frequency PLL2_LOCK_REG Registered PLL2 lock This is a one shot registered signal of the PLL2_LOCK signal It is only clea...

Page 141: ...atchdog Timer flag This bit is set if the Watchdog timer resets the system It is cleared by writing to the STFClr location It is reset to 0 CHIPID Chip ID bits This 8 bit register determines the Chip Identification for the device For the device this value is 0x20 CHIPMAN This 8 bit register determines the Chip Manufacturer ID for the device For the device this value is 0x43 PwrCnt Address 0x8093_0...

Page 142: ...een writing to this register bit and actually accessing the USB Host The number of cycles will depend on the setting of HCLK and PCLK division in the ClkSet1 and ClkSet2 register s This bit is also used to gate the 48 MHz and 12 MHz clocks to the USB Host block in order to save power It is reset to zero thus gating off the USB Host clocks By setting this to one the USB Host clocks are enabled At l...

Page 143: ... Standby location it must be immediately followed by 5 NOP instructions This is needed to flush the instruction pipeline in the ARM920T core Writes to these locations have no effect Bit Descriptions RSVD There are no readable bits in this register TEOI Address 0x8093_0018 Write Definition Writing to the TEOI location will clear the periodic Watchdog expired interrupt WEINT and the 64 Hz TICK inter...

Page 144: ...owed by 5 NOP instructions This is needed to flush the instruction pipeline in the ARM920T core Writing to this register will cause the the device to enter Standby for between 8 ms to 16 ms Reading from this register will not cause an entry into Standby mode Bit Descriptions RSVD Reserved Unknown During Read PLL1_X2IPD These 5 register bits set the input divider for PLL1 operation On power on rese...

Page 145: ...er on reset these bits are reset to 11b 3 decimal Note This means that PLL1 FOUT is programmed to be 36 864 000 Hz on startup Note The value in the register is the actual coefficient minus one PCLKDIV These two bits set the divide ratio between the HCLK AHB clock and the APB clock PCLK 00 Divide by 1 01 Divide by 2 10 Divide by 4 11 Divide by 8 On power on reset the value is set to 00b Note Care m...

Page 146: ...ese three bits set the divide ratio between the VCO output and processor clock On power on reset the value is set to 000b 000 Divide by 1 011 Divide by 8 001 Divide by 2 100 Divide by 16 010 Divide by 4 For FCLKDIV values equal to 1xxb except for 100b the divide ratio will be divide by 1 ClkSet2 Address 0x8093_0024 Read Write Definition The ClkSet2 register is used for setting the dividers interna...

Page 147: ...Note This means that PLL2 FOUT is programmed to be 48 000 000 Hz on startup Note The value in the register is the actual coefficient minus one PLL2_EN This bit enables PLL2 If set PLL2 is enabled If this bit is zero PLL2 is disabled On power on reset the value is set to 0b nBYP2 This bit selects the clock source for the processor clock dividers If set PLL2 is the clock source If this bit is set to...

Page 148: ...Bit Descriptions Value This is a 32 bit read write location APBWait Address 0x8093_0050 Read Write Definition The APBWait register controls the insertion of wait states for APB peripherals Bit Descriptions RSVD Reserved Unknown During Read NO_WRITE_WAIT Used in the AHB APB bridge to not insert an AHB wait during writes if set If reset a wait state is added by forcing HREADY 0 during ST_WRITE This ...

Page 149: ...elected by PRI_ORD after it is granted until one of the above masters is granted the bus and is placed on top of the priority scheme DMA_ENIRQ When set the arbiter will degrant DMA from the AHB bus and will ignore subsequent requests from DMA if an IRQ is active When IRQ is cleared the DMA request is allowed again There is no impact on other masters Reset to 0 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 150: ...asters Reset to 0 MAC_ENIRQ When set the arbiter will degrant Ethernet MAC from the AHB bus and will ignore subsequent requests from the MAC if an IRQ is active When IRQ is cleared the MAC request is allowed again There is no impact on other masters Reset to 0 MAC_ENFIQ When set the arbiter will degrant the Ethernet MAC from the AHB bus and will ignore subsequent requests from the MAC if an FIQ is...

Page 151: ...ix controller active ADCPD ADC Power Down 1 ADC and clocks are powered down 0 ADC and clocks are active ADCPD must be zero for normal touch screen operation and for direct ADC operation RAS Raster inactive 1 Disables video pixel clock to most of the Raster engine 0 Normal video clock to Raster engine RasOnP3 Raster On SDRAM Port 3 1 The Raster video refresh SDRAM accesses use the system primary AH...

Page 152: ...onIDE GPIO Port E on IDE pins 0 GPIO Port E used for IDE 1 GPIO Port E used for GPIO PonG PWM 1 output on EGPIO pin GonIDE GPIO Port G on IDE pins 0 GPIO Port G used for IDE 1 GPIO Port G used for GPIO HonIDE GPIO Port H on IDE pins Table 5 7 Audio Interfaces Pin Assignment Pin Name Normal Mode I2 S on SSP Mode I2 S on AC 97 Mode Pin Description Pin Description Pin Description SCLK1 SPI Bit Clock ...

Page 153: ...effect unless HC3EN is 0 1 pin EGPIO 3 is used for an HDLC clock with UART1 0 pin EGPIO 3 is not used TIN Touchscreen controller inactive 1 Touchscreen controller to inactive state 0 Touchscreen controller active To use the ADC converter independent of the Touch screen controller the Touchscreen controller must be enabled and set inactive The ADC can then be operated using the direct access regist...

Page 154: ...pins 0 Modem support signals do not use EGPIO 0 pins TonG TENn on GPIO This bit has no effect unless HC3EN and HC1EN are 0 1 UART3 TENn signal drives EGPIO 3 0 EGPIO 3 used by GPIO GonK GPIO on Key Matrix 1 Key Matrix pins are configured for GPIO operation 0 Key Matrix pins are controlled by other options The GonK has precedence over the Key Matrix controller The SPI0 when mapped to Key Matrix pin...

Page 155: ...vider ESEL External clock source select 0 use the external XTALI clock input as the clock source 1 use one of the internal PLLs selected by PSEL as the clock source PSEL PLL source select 1 select PLL2 as the clock source 0 select PLL1 as the clock source PDIV Pre divider value Generates divide by 2 2 5 or 3 from the clock source 00 Disable clock 01 Divide by 2 10 Divide by 2 5 11 Divide by 3 VDIV...

Page 156: ...lect 0 Use the external XTALI clock input as the clock source 1 Use one of the internal PLLs selected by PSEL as the clock source PSEL PLL source select 1 Select PLL2 as the clock source 0 Select PLL1 as the clock source PDIV Pre divider value Generates divide by 2 2 5 or 3 from the clock source 00 Disable clock 01 Divide by 2 10 Divide by 2 5 11 Divide by 3 MDIV MIR_CLK divider value Forms a divi...

Page 157: ...nored in slave mode ORIDE Override I2 S master configuration 1 Override the SAI_MSTR_CLK_CFG from the I2 S block and use the I2SClkDiv Register settings 0 Use the I2S SAI_MSTR_CLK_CFG signals DROP Drop SCLK clocks 1 When in 64x mode drop 8 SCLKs 0 Do not drop SCLKs SPOL SCLK polarity Defines the SCLK edge that aligns to LRCLK transitions 1 LRCLK transitions on the falling SCLK edge 0 LRCLK transit...

Page 158: ...om the clock source 00 Disable clock 01 Divide by 2 10 Divide by 2 5 11 Divide by 3 MDIV MCLK divider value Forms a divide by N of the pre divide clock output MCLK is the source clock divided by PDIV divided by N KeyTchClkDiv Address 0x8093_0090 Read Write Software locked Default 0x0000_0000 Definition Configures the Key Matrix Touchscreen and ADC clocks Touchscreen clock is a fixed divide by 4 fr...

Page 159: ...clock divider value 0 Key Matrix Clock is divide by 16 from the external oscillator 1 Key Matrix Clock is divide by 4 from the external oscillator CHIP_ID Address 0x8093_0094 Read Only Definition Chip ID register Bit Descriptions RSVD Reserved Unknown During Read REV Revision Reads chip Version number 0011 Rev D0 0100 Rev D1 0101 Rev E0 0110 Rev E1 0111 Rev E2 0 Reads zero ID 15 0 Chip ID Number r...

Page 160: ...01 Rev E0 SBOOT Serial Boot Flag 1 hardware detected Serial Boot selection 0 hardware detected Normal Boot This bit is read only LCSn7 LCSn6 Latched version of CSn7 and CSn6 respectively These are used to define the external bus width for the boot code LASDO Latched version of ASDO pin Used to select synchronous versus asynchronous boot device LEEDA Latched version of EEDAT pin LEECLK Define Inter...

Page 161: ...inition Syscon Software Lock Register Provides software control port for all Syscon locked registers Writing the LOCK field to 0xAA opens the lock Reading the register will return 0x0000_0001 when the lock is open and all zeros when the lock is closed locked Bit Descriptions RSVD Reserved Unknown During Read LOCK Lock code value This field must be written to a value of 0xAA to open the software lo...

Page 163: ...at the interrupt has been serviced allowing lower priority interrupts to go active Registers in the VIC use a bit position for each different interrupt source The bit position is fixed but the handling of each interrupt is configurable by the VIC Software can generate software interrupts by controlling each request line The VIC provides a software interface to the interrupt system Two levels of in...

Page 164: ...y followed by vectored interrupt 0 to vectored interrupt 15 Non vectored IRQ interrupts have the lowest priority Any of the non vectored Interrupts can be either FIQ or IRQ the interrupt type is determined by programming the appropriate register VICxIntSelect on page 6 11 Vector Address and Priority Logic Vector Address and Priority Logic VIC Daisy Chain VICINTSOURCE 63 32 IRQ from VIC1 Vector Add...

Page 165: ... interrupt Timer Counter 1 5 TC2UI TC2 under flow interrupt Timer Counter 2 6 AACINTR Advanced Audio Codec interrupt 7 DMAM2P0 DMA Memory to Peripheral Interrupt 0 8 DMAM2P1 DMA Memory to Peripheral Interrupt 1 9 DMAM2P2 DMA Memory to Peripheral Interrupt 2 10 DMAM2P3 DMA Memory to Peripheral Interrupt 3 11 DMAM2P4 DMA Memory to Peripheral Interrupt 4 12 DMAM2P5 DMA Memory to Peripheral Interrupt ...

Page 166: ...Interrupt 36 WEINT Watchdog Expired Interrupt 37 INT_RTC RTC Interrupt 38 INT_IrDA IrDA Interrupt 39 INT_MAC Ethernet MAC Interrupt 40 Reserved 41 INT_PROG Raster Programmable Interrupt 42 CLK1HZ 1 Hz Clock Interrupt 43 V_SYNC Video Sync Interrupt 44 INT_VIDEO_FIFO Raster Video FIFO Interrupt 45 INT_SSP1RX SSP Receive Interrupt 46 INT_SSP1TX SSP Transmit Interrupt 47 Reserved 48 Reserved 49 Reserv...

Page 167: ...eripheral to Memory Channel 2 Interrupt See Chapter 10 DMA Controller DMAM2P3 Internal Memory to Peripheral and Peripheral to Memory Channel 3 Interrupt See Chapter 10 DMA Controller DMAM2P4 Internal Memory to Peripheral and Peripheral to Memory Channel 4 Interrupt See Chapter 10 DMA Controller DMAM2P5 Internal Memory to Peripheral and Peripheral to Memory Channel 5 Interrupt See Chapter 10 DMA Co...

Page 168: ... derived from a 15 stage ripple counter that divides the 32 768kHz oscillator input down to 1Hz for the real time clock This interrupt is cleared by writing any value to the RTCSts register See Chapter 20 Real Time Clock With Software Trim WEINT Watchdog Expired Interrupt This interrupt will become active on a rising edge of the periodic 64Hz tick interrupt clock if the TICK interrupt TINT is stil...

Page 169: ...This interrupt is active if any UART1 interrupt is active Interrupt service routines will need to read the relevant status bits within UART1 to determine the source of the interrupt All these sources are individually maskable within UART1 See Chapter 15 UART1 SSPINTR Synchronous Serial Port SSP Interrupt See Chapter 23 Synchronous Serial Port INT_UART2 UART 2 General Interrupt This interrupt is ac...

Page 170: ...ster VIC base 0030 Read Write 32 0x0000_0000 VICxVectAddr Vector address register VIC base 0034 Read Write 32 0x0000_0000 VICxDefVectAddr Default vector address register VIC base 0100 Read Write 32 0x0000_0000 VICxVectAddr0 Vector address 0 register VIC base 0104 Read Write 32 0x0000_0000 VICxVectAddr1 Vector address 1 register VIC base 0108 Read Write 32 0x0000_0000 VICxVectAddr2 Vector address 2...

Page 171: ...0220 Read Write 6 0x00 VICxVectCntl8 Vector control 8 register VIC base 0224 Read Write 6 0x00 VICxVectCntl9 Vector control 9 register VIC base 0228 Read Write 6 0x00 VICxVectCntl10 Vector control 10 register VIC base 022C Read Write 6 0x00 VICxVectCntl11 Vector control 11 register VIC base 0230 Read Write 6 0x00 VICxVectCntl12 Vector control 12 register VIC base 0234 Read Write 6 0x00 VICxVectCnt...

Page 172: ...tus Address VIC1FIQStatus 0x800B_0004 Read Only VIC2FIQStatus 0x800C_0004 Read Only Definition FIQ Status Register The VICxFIQStatus register provides the status of the interrupts after FIQ masking Bit Descriptions FIQStatus Shows the status of the interrupts after masking by the VICxIntEnable and VICxIntSelect registers A 1 indicates that the interrupt is active and generates an interrupt to the ...

Page 173: ...0x800B_000C Read Write VIC2IntSelect 0x800C_000C Read Write Definition Interrupt Select Register The VICxIntSelect register selects whether the corresponding interrupt source generates an FIQ or an IRQ interrupt Bit Descriptions IntSelect Selects type of interrupt for interrupt request 1 FIQ interrupt 0 IRQ interrupt VICxIntEnable Address VIC1IntEnable 0x800B_0010 Read Write VIC2IntEnable 0x800C_0...

Page 174: ...ly VIC2IntEnClear 0x800C_0014 Write Only Default Don t Care Definition Interrupt Enable Clear Register The VICxIntEnClear register clears bits in the VICxIntEnable register Bit Descriptions IntEnable Clear Clears bits in the VICxIntEnable register Writing a bit to 1 clears the corresponding bit in the VICxIntEnable register Any bits written to 0 have no effect VICxSoftInt Address VIC1SoftInt 0x800...

Page 175: ...ftIntClear 0x800C_001C Write Only Default Don t Care Definition Software Interrupt Clear Register The VICxSoftIntClear register clears bits in the VICxSoftInt register Bit Descriptions SoftIntClear Clears bits in the VICxSoftInt register Writing a bit to 1 clears the corresponding bit in the VICxSoftInt register Writing a bit to 0 has no effect VICxProtection Address VIC1Protection 0x800B_0018 Rea...

Page 176: ...tains the Interrupt Service Routine ISR address of the currently active interrupt Note Reading from this register provides the address of the ISR and indicates to the priority hardware that the interrupt is being serviced Writing to this register indicates to the priority hardware that the interrupt has been serviced The register should be used as follows The ISR reads the VICxVectAddr register wh...

Page 177: ...ters read only the VIC registers that are needed Bit Descriptions VectorAddr Contains the address of the currently active ISR Any writes to this register clear the interrupt VICxDefVectAddr Address VIC1DefVectAddr 0x800B_0034 Read Write VIC2DefVectAddr 0x800C_0034 Read Write Definition Default Vector Address Register The VICxDefVectAddr register contains the default ISR address Bit Descriptions De...

Page 178: ...18 Read Write VIC1VectAddr7 0x800B_011C Read Write VIC1VectAddr8 0x800B_0120 Read Write VIC1VectAddr9 0x800B_0124 Read Write VIC1VectAddr10 0x800B_0128 Read Write VIC1VectAddr11 0x800B_012C Read Write VIC1VectAddr12 0x800B_0130 Read Write VIC1VectAddr13 0x800B_0134 Read Write VIC1VectAddr14 0x800B_0138 Read Write VIC1VectAddr15 0x800B_013C Read Write VIC2VectAddr0 0x800C_0100 Read Write VIC2VectAd...

Page 179: ...0x800C_0134 Read Write VIC2VectAddr14 0x800C_0138 Read Write VIC2VectAddr15 0x800C_013C Read Write Definition Vector Address Registers The 32 VICxVectAdd0 through VICxVectAdd15 registers contain the ISR vector addresses that is the addresses of the ISRs for the particular 16 interrupts that are vectored Bit Descriptions VectorAddr Contains ISR vector address VICxVectCntl0 VICxVectCntl1 VICxVectCnt...

Page 180: ...1VectCntl15 0x800B_023C Read Write VIC2VectCntl0 0x800C_0200 Read Write VIC2VectCntl1 0x800C_0204 Read Write VIC2VectCntl2 0x800C_0208 Read Write VIC2VectCntl3 0x800C_020C Read Write VIC2VectCntl4 0x800C_0210 Read Write VIC2VectCntl5 0x800C_0214 Read Write VIC2VectCntl6 0x800C_0218 Read Write VIC2VectCntl7 0x800C_021C Read Write VIC2VectCntl8 0x800C_0220 Read Write VIC2VectCntl9 0x800C_0224 Read W...

Page 181: ...Enable register and the interrupt is set to generate an IRQ interrupt in the VICxIntSelect register This prevents multiple interrupts being generated from a single request if the controller is incorrectly programmed Bit Descriptions RSVD Reserved Unknown During Read E Enables vector interrupt This bit is cleared to 0 on reset IntSource Selects interrupt source by number You can select any of the 3...

Page 183: ... All control register accesses are memory mapped as single word values and cannot be accessed as 8 bit or 16 bit memory values The Raster engine also provides hardware accelerated cursor support The cursor size is programmable up to 64 pixels wide by 64 pixels in height and it can be stored anywhere in memory as a 2 bpp bitmap image The Raster Cursor accesses system memory to fetch the cursor imag...

Page 184: ...Rate Hz Notes VFD 128 x 32 2 4 bpp Monochrome 8 0 25 400 LCD 128 x 64 2 4 bpp Monochrome 4 0 5 230 Parallel Command Word interface LCD 256 x 128 2 4 bpp Monochrome 4 0 5 60 QVGA TFT LCD 320 x 234 6 4 8 bpp Analog 1 6 4 80 QVGA STN LCD 320 x 240 4 4 bit RGB 4 bit RGB 1 4 50 HVGA STN LCD 640 x 240 8 4 bit RGB 4 bit RGB 1 8 50 VGA DC Plasma 640 x 400 16 4 bpp Monochrome 4 4 60 VGA EL 640 x 480 24 4 o...

Page 185: ...hat can be used to provide a DC voltage level for brightness control Hardware cursor support with bottom and right edge clipping performed by hardware 24 bit color depth but only 18 bits is bond out 7 3 Raster Engine Features Overview 7 3 1 Hardware Blinking The raster engine pipeline contains hardware pixel blinking logic This circuitry will blink pixels based on the Rate field in the BlinkRate r...

Page 186: ...sed on frame count screen location and pixel value For grayscale displays the pixel gray appearance is determined by 3 bits of the pixel data For color depth expansion on LCD displays the pixel color appearance is determined by 3 bits each from the red green and blue portions of the pixel data 7 3 4 Frame Buffer Organization The Raster Engine is designed to support video information as DIB Device ...

Page 187: ... bit 0 Byte 0 Byte1 Byte 2 Byte 3 Pixel 3 Pixel 2 Pixel 1 Pixel 0 32 bit Word 15 or 16 bits per pixel 32 bit Word Pixel 0 Pixel 1 Byte 3 Byte 2 Byte1 Byte 0 bit 15 bit 8 bit 7 bit 0 bit 31 bit 24 bit 23 bit 16 bit 31 bit 24 bit 23 bit 16 bit 15 bit 8 bit 7 bit 0 Byte1 Byte 0 Byte 3 Byte 2 Pixel 1 Pixel 0 32 bit Word 24 bits per pixel packed 32 bit Word 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 Byte 3 Byte...

Page 188: ... bit 16 bit 15 bit 8 bit 7 bit 0 bit 23 bit 16 bit 23 bit 16 bit 23 bit 16 bit 23 bit 16 Unused Pixel 0 Red Pixel 0 Green Pixel 0 Blue Byte 2 Byte 6 Byte B Byte E Word 0 Word 1 Word 2 Word 3 32 bit Word 1 Green Green Green Green Byte 7 Byte 6 Byte 5 Byte 4 bit 15 bit 8 bit 15 bit 8 bit 15 bit 8 bit 15 bit 8 bit 31 bit 24 bit 23 bit 16 bit 15 bit 8 bit 7 bit 0 Byte 1 Byte 5 Byte A Byte D Unused Pix...

Page 189: ...cursor color 2 The cursor hardware must be supplied this information Image starting address Two cursor colors An X screen location and a Y screen location A cursor size Using this information the hardware overlays the cursor in the output video stream Bottom and right edge clipping is performed by hardware Some extra calculations and register setups are required for cursor support during dual scan...

Page 190: ...low the FIFOLevel again the image reading process from the frame buffer continues Note FIFOLevel values of greater than 16 words are not recommended due to the possibility of FIFO underflow For dual scan operation the FIFO is split into two halves where each halve operates with a separate FULL indicator In dual scan mode selected by writing DSCAN 1 to the PixelMode register the FULL and DS_FULL in...

Page 191: ...defines the word offset in memory between the beginning of each line and the next line Setting the VLineStep value larger than the LineLength value provides the capability for image panning as shown in Figure 7 2 Figure 7 2 Video Buffer Diagram 7 4 2 Video FIFO The video FIFO is used to buffer data transferred from the image memory to the Video output circuitry without stalling the video data stre...

Page 192: ... at the same programmed frequency The most flexible way to blink pixels is to use a look up table LUT This is done by logically transforming the address into the look up table based on whether the pixel is a blink pixel and whether it is currently in the blink state For example a red blinking pixel may be set up to normally address location 0x11 in the look up table When not in the blink state the...

Page 193: ...e AHB Changing the SWITCH bit in the LUTSwCtrl register toggles which LUT is in the pipe and which is accessible by the AHB The LUTs are mapped to memory addresses and are accessible from the AHB one at a time During active video display the LUT switch command is synchronized to the beginning of the next vertical frame When the video state machine is disabled the LUT switch occurs almost immediate...

Page 194: ... up to 9 bits wide each 18 pixel data lines active 4 pixels per clock up to 4 bits wide each 16 pixel data lines active or 8 pixels per clock up to 2 bits wide each 16 pixel data lines active The interface can be programmed to output 2 2 3 3 bit pixels on the lower 8 bits of the bus per pixel clock The interface can be programmed to operate in dual scan 2 2 3 pixel mode placing 2 2 3 pixels from t...

Page 195: ...7 Lower P 22 R 6 Lower P 21 R 5 Lower P 15 G 7 Lower P 14 G 6 Lower P 13 G 5 Lower P 7 B 7 Lower P 6 B 6 Lower P 5 B 5 Upper P 23 R 7 Upper P 22 R 6 Upper P 21 R 5 Upper P 15 G 7 Upper P 14 G 6 Upper P 13 G 5 Upper P 7 B 7 Upper P 6 B 6 Upper P 5 B 5 0x3 0x0 0x8 progressive scan 4 pixels per shift clock dual scan P3 14 G3 6 P3 6 B3 6 P2 14 B2 6 P2 6 B2 6 P1 14 G1 6 P1 6 B1 6 P0 14 G0 6 P0 6 B0 6 P...

Page 196: ...e 0x6 0x0 0x8 dual 2 2 3 pixels per clock X X X X X X X X L G2 L B2 L R1 L G1 L B1 L R0 L G0 L B0 U G2 U B2 U R1 U G1 U B1 U R0 U G0 U B0 X X X X X X X X L B5 L R4 L G4 L B4 L R3 L G3 L B3 L R2 U B5 U R4 U G4 U B4 U R3 U G3 U B3 U R2 X X X X X X X X L R7 L G7 L B7 L R6 L G6 L B6 L R5 L G5 U R7 U G7 U B7 U R6 U G6 U B6 U R5 U G5 CCIREN subs D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 LCDEN subs XECL YSCL ACEN ...

Page 197: ...and vertical The grayscale circuits are inserted into the video pipeline after the color LUT The circuitry takes three bits from the output of the color LUT one from each color and uses them as the inputs for the grayscale LUT These three bits are then processed by the grayscale circuitry to generate a new three bit output based on the configuration of the grayscale LUT The three bit output of the...

Page 198: ...s manipulated as it is being displayed on the screen 7 4 8 4 HORZ_CNTx pixel timing This timing is controlled by the HORZ_CNTx counter and will indicate what pixel count values will cause a given pixel to be turned on It is possible to have a pixel turned on for all HORZ counts zero HORZ counts or a defined pattern of HORZ counts This counter is incremented by the pixel clock 7 4 8 5 VERT_CNTx lin...

Page 199: ...2 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01 011 X X X base B0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01 100 X X X base B4 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01 101 X X X base B8 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01 110 X X X base BC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 01 111 X X X base C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 000 X X X base C4 D15 D14 ...

Page 200: ...nter registers set up for 4 counts The last column shows which register is used to retrieve the look up value and the bit position within that register that is used as the source to send to the COLORMUX for the given clock Clocks 4 9 14 and 19 represent all remaining pixels on the line Clocks 24 and 29 represent all remaining pixels for the frame These entries will keep this example table to a man...

Page 201: ... base f4 D1 32 2 0 3 5 base f4 D2 33 3 0 3 5 base f4 D3 Table 7 6 Programming Format Fra me Ve rt Ho rz VCNT lines 11 11 11 11 10 10 1 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 GrySclLU T Address 4 Ctr Ct r Ctr HCNT pixels 11 10 01 00 11 10 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 Frame Pix el D18 D 17 D1 6 register address D 15 D 14 D 13 D 12 D 11 D1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Val ue X ...

Page 202: ... a 4Hx4Vx4F as shown in Figure 7 3 However we effectively halved the refresh rate of these pixels and depending on the refresh rate of the display are likely to see flickering for this shade Figure 7 3 Graphics Matrix for 50 Duty Cycle To avoid flickering it is better to play a spatial trick and turn on every other pixel so that the eye integrates the on and off pixels between two consecutive fram...

Page 203: ...is may create another type of apparent image distortion referred to as a walking pattern One of the matrix indices may need to be changed to count by 3 to eliminate this combination of temporal and spatial distortion Figure 7 5 Sample Matrix That Avoids Flickering Frame 0 H O R Z Frame 1 V 1 0 1 0 0 1 0 1 E 1 0 1 0 0 1 0 1 R 1 0 1 0 0 1 0 1 T 1 0 1 0 0 1 0 1 Frame 2 Frame 3 1 0 1 0 0 1 0 1 1 0 1 0...

Page 204: ...ted and given the three frame interval any cell in the matrix should only be active for one frame The matrix could be filled in as in Figure 7 6 Figure 7 6 Programming for One third Luminous Intensity Table 7 7 Programming 50 Duty Cycle Into Lookup Table Frame Vert Horz VCNT lines 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 GrySclLUT Address 4 Ctr Ctr Ctr HCNT pixels 1 1 1 0 0 ...

Page 205: ...e used to program this pattern into the grayscale look up table In this mode the X locations are ignored by the grayscale generation Finally just for demonstration purposes a matrix with mixed 3 and 4 count axes is shown in Figure 7 8 Frame 0 H O R Z Frame 1 V 1 0 0 0 1 0 E 0 0 1 0 1 0 R 0 1 0 0 0 1 T Frame 2 0 0 1 1 0 0 1 0 0 Table 7 8 Programming 33 Duty Cycle into the Lookup Table Frame Vert Ho...

Page 206: ...ine at a time from memory and multiplexes the video stream data based on the cursor values The X and Y locations are compared to the horizontal and vertical counters and trigger the state machine to enable the cursor output overlay Frame 0 H O R Z Frame 1 V 1 0 0 0 0 1 0 0 E 0 0 1 1 0 1 0 0 R 0 1 0 0 0 0 1 1 T Frame 2 0 0 1 1 1 0 0 1 1 0 0 0 Table 7 9 Programming 33 Duty Cycle into the Lookup Tabl...

Page 207: ...jump to the reset value The cursor will then continue to be overlaid when the Y location is reached and will jump to the start address value when the height counter for the upper half generates a carry Offsetting these values and changing the width of the cursor to be different from the cursor step value allows the right 48 32 or 16 pixels of a larger cursor to be displayed only Furthermore offset...

Page 208: ...tion value will not be used until the next frame The hardware cursor circuitry has a separate blinking function The rate is a 50 duty cycle programmable number of vertical frame intervals When a blink frame is active the color RGB mux switches in 24 bit CursorBlinkColor1 or CursorBlinkColor2 values for CursorColor1 or CursorColor2 respectively 7 4 9 1 Registers Used for Cursor The registers used f...

Page 209: ...0x3 11 binary 7 4 9 1 6 CursorXYLoc Register This register provides the place in the X and Y position of the image where the cursor should be inserted The X position is represented by the XLOC bits and the Y position is represented by the YLOC bits in the CursorXYLoc register The XLOC bits and YLOC bits are compared with the respective counter YLOC is the line counter XLOC is the pixel counter The...

Page 210: ...creen image location automatically change at this time under hardware control The interval for making LUT changes etc without affecting the displayed image depends on the display s technology The time duration is equal to the vertical blanking interval VLinesTotal duration VACTIVE duration In addition the programmable VCLR and HCLR fields in the SigClrStr register are used as a secondary interrupt...

Page 211: ...Porch Horizontal Active Video LINECARRY CLKS VLINESTOTAL VACTIVESTRT VACTIVESTOP VSYNCn VACTIVE HSYNCn HACTIVE 0h 0h 1h VLINESTOTAL VLINESTOTAL VLINESTOTAL 1 Vertical down counter 0h 0h 1h HCLKSTOTAL HCLKSTOTAL HCLKSTOTAL 1 Horizontal down counter VSYNCSTART VSYNCSTOP SPCLK DURING Vertical VCLKSTOP VCLKSTART Vertical Sync Interval HACTIVESTRT HACTIVESTOP HSYNCSTART HSYNCSTOP HCLKSTOP HCLKSTART SPC...

Page 212: ...ACTIVESTRT VSYNCn VACTIVE HSYNCn HACTIVE 0h 0h 1h VLINESTOTAL VLINESTOTAL Vertical down counter 0h 0h 1h HCLKSTOTAL HCLKSTOTAL HCLKSTOTAL 1 Horizontal down counter VSYNCSTART VSYNCSTOP SPCLK DURING Vertical VCLKSTRT VCLKSTOP HACTIVESTRT HACTIVESTOP HSYNCSTART HSYNCSTOP HCLKSTOP HCLKSTART SPCLK DURING Horizontal VBLANKn VBLANKSTOP VBLANKSTRT HBLANKn HBLANKSTRT HBLANKSTOP VACTIVESTOP VLINESTOTAL 2 C...

Page 213: ...e is 0x7FF for 2048 lines 7 4 10 1 3 Setting up the LineLength Register The LineLength register contains the number of 32 bit words that the Raster Engine must fetch from SDRAM for each scan line This value is always one less than the needed number of 32 bit words because a programmed value of 0x0 specifies a single 32 bit word For example a display width of eighty 8 bit pixels requires that twent...

Page 214: ...s controlled by the BlinkRate register All blinking pixels blink at the same rate 7 4 11 1 BlinkRate This value is used to control the number of video frames that occur before the pixel value that is assigned to blink is switched between its non blinked and blinked values The actual rate is calculated by Blink cycle 2 x 1 VCLK x HClkTotal x VLinesTotal x 255 BlinkRate where VCLK is the basic clock...

Page 215: ...ng MSBs in the BlinkPattrn register are 10 and the two MSBs of the pixel value are 10 then the pixel of value 0xAF is a blink pixel In fact all pixel values of 10xx_xxxx are blink pixels If BlinkPattrn was changed to 0x0000_0048 above a pixel of value 0xAF would not be a blink pixel 7 4 11 2 3 BlinkMask Register The BlinkMask register is only used if the blink mode definition bits M 3 0 in the Pix...

Page 216: ... LUT blinking 0100 Background Blinking The pixel data is replaced with the value in the BkgrndOffset register and the new pixel value is placed into the pipeline and sent to the Color Mux 0101 Offset Single Blinking The pixel data is manipulated by adding the value of the BkgrndOffset register with the pixel data The resulting pixel data will be placed into the pipeline and then sent to the Color ...

Page 217: ...AM that is used as pixel look up table LUT for pixel depths up to 8 bits Appropriate blink operations if any are performed on the pixel data fetched from the video memory and the resulting pixel data value is used as an index into the LUT The pixel value located at the index position continues through the video pipeline The LUT is memory mapped and may be written at any time However if it is writt...

Page 218: ...6 bits PWM brightness control 0x8003_0024 VideoAttribs Write Read Write 16 bits Video state machine parameters 0x8003_0028 VidScrnPage No Read Write 32 bits Starting address of video screen 0x8003_002C VidScrnHPage No Read Write 32 bits Starting address of video screen half page 0x8003_0030 ScrnLines No Read Write 11 bits Number of active lines scanned to the screen 0x8003_0034 LineLength No Read ...

Page 219: ...24 bits Color when cursor value is 11 and cursor is in blink state 0x8003_0224 CursorBlinkRateCtrl No Read Write 1 8 bits Enable and rate for cursor blinking 0x8003_007C RasterSWLock Read Read Write 8 bits Software Lock register This register unlocks registers that have a SWLOCK 0x8003_0080 0x8003_00FC GrySclLUTR No Read Write 32 x 19 Grayscale matrix Red 0x8003_0200 VidSigRsltVal No Read Only 16 ...

Page 220: ...number of horizontal lines for a video frame including synchronization blanking and active lines This value is used to preset the Vertical down counter Please refer to video the signalling timing diagrams shown in Figure 7 9 and Figure 7 10 VSyncStrtStop Address 0x8003_0004 Default 0x0000_0000 Definition Vertical Sync Pulse Start Stop register Bit Descriptions RSVD Reserved Unknown during read STO...

Page 221: ...ring read STOP Stop Read Write The STOP value is the value of the Vertical down counter at which the VACTIVE signal becomes inactive stops This indicates the end of the active video portion for the Vertical frame Please refer to the video signalling timing diagrams in Figure 7 9 and Figure 7 10 VACTIVE is an internal block signal The active video interval is controlled by the logical OR of VACTIVE...

Page 222: ...he Vertical frame Please refer to video signalling timing diagrams in Figure 7 9 and Figure 7 10 VBLANKn is an internal block signal The NBLANK output is a logical AND of NVBLANK and HBLANKn STRT Start Read Write The STRT value is the value of the Vertical down counter at which the VBLANKn signal becomes active starts This is used to generate the BLANKn signal that is used by external devices and ...

Page 223: ...me Please refer to video signalling timing diagrams in Figure 7 9 and Figure 7 10 VCLKEN is an internal block signal The SPCLK output is enabled by the logical AND of VCLKEN and HCLKEN STRT Start Read Write The STRT timing register contains the value of the Vertical down counter at which the VCLKEN signal becomes active starts This indicates the start of the video clock for the Vertical frame Plea...

Page 224: ...of clocks for a horizontal video line including synchronization blanking and active clocks This value is used to preset the Horizontal down counter Please refer to video signalling timing diagrams in Figure 7 9 and Figure 7 10 HSyncStrtStop Address 0x8003_0014 Default 0x0000_0000 Definition HorizontaL Sync Start Stop Register Bit Descriptions RSVD Reserved Unknown during read STOP Stop Read Write ...

Page 225: ...re 7 10 HActiveStrtStop Address 0x8003_0018 Default 0x0000_0000 Definition Horizontal Active period Start Stop register Note When horizontal clock gating is required set the STRT and STOP fields in the HActiveStrtStop register to the STRT and STOP values in HClkStrtStop 5 This is a programming requirement that is easily overlooked Bit Descriptions RSVD Reserved Unknown during read STOP Stop Read W...

Page 226: ...he Horizontal down counter at which the HBLANK signal becomes inactive stops This is used to generate the BLANKn signal that is used by external devices to indicate the end of the active video portion for the Horizontal line Please refer to video signalling timing diagrams in Figure 7 9 and Figure 7 10 HBLANK is an internal clock signal The BLANKn output is a logical AND of VBLANK and HBLANK STRT ...

Page 227: ...t which the HCLKEN signal becomes inactive stops This indicates the end of the video clock for the Horizontal frame Please refer to video signalling timing diagrams in Figure 7 9 and Figure 7 10 HCLKEN is an internal clock signal The SPCLK output is enabled by the logical AND of VCLKEN and HCLKEN STRT Start Read Write The STRT value is the value of the Horizontal down counter at which the HCLKEN s...

Page 228: ...AM of the upper left corner of the video screen to be scanned out The absolute AHB address for the video screen page is determined by the combination of this bit field as well as the SDSEL bit held in the VideoAttribs register NA Not Assigned Will return written value during a read VidScrnHPage Address 0x8003_002C Default 0x0000_0000 Definition Video Screen Half Page Register Bit Descriptions RSVD...

Page 229: ...rnLines Address 0x8003_0030 Default 0x0000_0000 Definition Video Screen Lines Register Bit Descriptions RSVD Reserved Unknown during read LINES Lines Read Write The Lines value written to this field specifies the number of lines to be scanned to the display during normal and half page mode operation LineLength Address 0x8003_0034 Default 0x0000_0000 Definition Video Line Length Register Bit Descri...

Page 230: ...but will exit the pipeline during the blanking interval When the end of LEN is reached STEP in the VLineStep register is added to the address for video data VLineStep Address 0x8003_0038 Default 0x0000_0000 Definition Video Line Step Size Register Bit Descriptions RSVD Reserved Unknown during read STEP Step Read Write When the end of the video line is reached see LEN in LineLength register the Ste...

Page 231: ...ical and horizontal video signals Please refer to the video signalling timing diagrams in Figure 7 9 and Figure 7 10 EOLOffset Address 0x8003_0230 Default 0x0000_0000 Definition End of line Offset Register Bit Descriptions RSVD Reserved Unknown during read OFFSET Offset Read Write The Offset value written to this field is added to the address at the end of every other video line if the Offset valu...

Page 232: ...CNT below that is when the brightness signal to the BRIGHT pin is 1 or 0 CNT Count Read Write The Count value written to this field specifies the number of horizontal lines counted during a brightness waveform period The counter counts down from the Count value to 0x0 The CNT value and the CMP value are used to construct a brightness control waveform on the BRIGHT pin by this relationship When Cou...

Page 233: ... Pixel Data Read Write Writing BKPXD 1 forces the pixel data on the P 17 0 pins to be 0x0 when the blanking signal on the BLANK pin is 0 0 Disable 1 Enable This allows the use of an inexpensive external DAC that does not contain data blanking logic DVERT Double Vertical Read Write Writing DVERT 1 forces the values of the defined bit fields in the VLinesTotal VSyncStrtStop VActiveStrtStop VBlankStr...

Page 234: ...ion pulses to be inserted into the composite synchronization signal on the V_CSYNC pin 0 Disable 1 Enable INTRLC Interlace Read Write Writing INTRLC 1 enables interlaced frame timing 0 Disable 1 Enable INT Interrupt Read Write If INTEN 1 an INT 1 status indicates that the end of active video interrupt has occurred 0 No interrupt 1 Interrupt occurred Write 0 to clear write 1 to test INTEN Interrupt...

Page 235: ...le Read Write The value written to this bit specifies the function of the signals to the P 16 pin and P 15 pin 0 Pixel data bits 16 and 15 are routed to pins P16 and P15 respectively 1 XECL and YSCL signals are routed to pins P16 and P15 respectively The XECL and YSCL signals are used to enable LCD drivers and register shifting ACEN AC Enable Read Write Writing ACEN 1 routes an LCD AC Waveform to ...

Page 236: ...V CPOL Vertical Composite Polarity Read Write The value written to this bit selects the polarity of the synchronization signal on the V_CSYNC pin 0 V_CSYNC is active LOW default 1 V_CSYNC is active HIGH CSYNC Composite Sync Read Write The value written to this bit selects whether the Vertical Sync or the Composite Sync signal is routed to the V_CSYNC pin 0 Vertical Sync 1 Composite Sync DATEN Pixe...

Page 237: ...whether the video state machine is enabled or not 0 Video state machine off 1 Video state machine enabled RasterSWLock Address 0x8003_007C Default 0x0000_0000 Definition Raster Software Lock register Bit Descriptions RSVD Reserved Unknown during read SWLCK Software Lock Read Write WRITE Writing 0X0000_00AA to this register will unlock all locked registers until the next block access READ During a ...

Page 238: ... LCD bias signal is to toggle Care must be taken when choosing this value while using the grayscale dithering algorithms as a DC build up may occur if the pixel timing for the on state of the pixel is concurrent with the bias frequency FIFOLevel Address 0x8003_0234 Default 0x0000_0010 Definition FIFO Refill Level register Bit Descriptions RSVD Reserved Unknown during read LEVEL Level Read Write 31...

Page 239: ... visual defects PixelMode Address 0x8003_0054 Default 0x0000_0000 Definition Pixel Mode register Bit Descriptions RSVD Reserved Unknown during read 0 Must be written as 0 TRBSW Two and Two Thirds Red Blue Swap Read Write Writing a Two and two thirds Red Blue Swap value to this bit selects the ordering of Red and Blue pixels for data shifted displays 0 Normal Blue is the low order bits followed by ...

Page 240: ...halves of the screen to be scanned out at the same time However dual scan mode could also be used to drive two separate synchronized displays each with different data 0 Single Scan full page 1 Dual Scan two half pages C Color Read Write The Color Mode is specified by selecting a value from Table 7 13 and writing it to this field M Mode Read Write The Blink Mode is specified by selecting a value fr...

Page 241: ... value mode 1 1 0 1 Blink brighter single value mode 1 1 1 0 Blink dimmer 888 mode 555 565 1 1 1 1 Blink brighter 888 mode 555 565 Table 7 15 Output Shift Mode Table S2 S1 S0 Shift Mode 0 0 0 1 pixel per pixel clock up to 24 bits wide 0 0 1 1 pixel mapped to 18 bits each pixel clock 0 1 0 2 pixels per shift clock up to 9 bits wide each 0 1 1 4 pixels per shift clock up to 4 bits wide each 1 0 0 8 ...

Page 242: ...nterface write cycle writing a 1 will initiate a parallel interface read cycle 1 Start Smart Panel write cycle 0 Start Smart Panel read cycle DAT Data Write Only The value written to this field is output on the parallel interface pins during a write cycle Writing PIFEN 1 to the VideoAttribs register redefines the signals on these pins for Parallel Interface Smart Panel operation V_CSYNC D7 Smart P...

Page 243: ...ould be written to this field When the parallel interface counter counts down to this value during a write cycle see RD bit in the ParllIfOut register for write cycle the E enable signal on the E pin goes active The E enable signal becomes inactive just before the counter counts down to 0x0 although data remains driven on the D 7 0 pins throughout the 0x0 count This allows data to be driven for on...

Page 244: ... pin DAT Data Read Only This parallel interface data is input to the EP93xx processor from the Smart Panel during a read cycle see RD bit in the ParllIfOut register for read cycle The D 7 0 bits from the Smart Panel are loaded into this DAT field respectively on the falling edge of the E enable control signal on the E pin Writing PIFEN 1 to the VideoAttribs register redefines the signals on these ...

Page 245: ...resses assigned to blink change between masked and unmasked see Blink Function on page 7 10 The on off blink cycle is controlled by this equation Blink Cycle 2 x 1 VCLK x HClkTotal x VLinesTotal x 255 BlinkRate BlinkMask Address 0x8003_0044 Default 0x0000_0000 Definition Blink Mask register This register is used in conjunction with the BlinkPattrn register to determine which pixels that are fetche...

Page 246: ...g modifies the LUT address by clearing bits ORing modifies the LUT address by setting bits XORing modifies the LUT address by inverting bits BlinkPattrn Address 0x8003_0048 Default 0x0000_0000 Definition Blink Pattern register This register is used in conjunction with the BlinkMask register to determine which pixels that are fetched from SDRAM are blink pixels see BlinkPattrn Register on page 7 33...

Page 247: ... Mask value that is written to this field defines which bits of the PATRN field in the BlinkPattrn register are used to validate a blink pixel 0 Bit used for comparison 1 Bit not used for comparison BkgrndOffset Address 0x8003_0050 Default 0x0000_0000 Definition Blink Background Color Blink Offset value register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD PMASK 15 14 13 12 11 10 9 8 7 6 5...

Page 248: ...d defines the mathematical offset value for the blink color The format for the mathematical offset is based on the color display mode that is 888 565 555 see Types of Blinking on page 7 33 Hardware Cursor Registers CursorAdrStart Address 0x8003_0060 Default 0x0000_0000 Definition Cursor Image Address Start register Bit Descriptions ADR Address Read Write The Cursor Address Start value that is writ...

Page 249: ...ons will be the same Otherwise the cursor will start being overlaid on the video information at the start address and when the dual scan height counter generates a carry will jump to the reset value The cursor will then continue to be overlaid when the Y location is reached and will jump to the start address value when the height counter for the upper half generates a carry Offsetting the reset va...

Page 250: ...pecifies the counter step size for the width of the cursor image 00 Step by 1 word or 16 pixels at a time 01 Step by 2 words or 32 pixels at a time 10 step by 3 words or 48 pixels at a time 11 Step by 4 words or 64 pixels at a time CLINS Cursor Lines Read Write The Cursor Lines value that is written to this field specifies the height in lines of the cursor image The value should be set to number o...

Page 251: ...s RSVD Reserved Unknown during read COLOR Color Read Write The Color value that is written to this field specifies the cursor image color that is inserted directly into the video pipeline This color overlays all other colors when the cursor is enabled This color does not go through the LUT The 2 bits per pixel cursor image is stored anywhere in SDRAM When cursor pixels are fetched from SDRAM they ...

Page 252: ...bottom of the screen To prevent cursor distortion a new Y Location value will not be used until the next frame CEN Cursor Enable Read Write Writing a 1 to this bit enables the hardware to insert the defined cursor into the image output video stream The cursor image fetched from an SDRAM location that is defined by the CursorAdrStart register is combined with the output video stream Writing a 0 to ...

Page 253: ...ixelMode register The cursor hardware will clip the cursor at the right edge of the screen To prevent cursor distortion a new X Location value will not be used until the next frame CursorDScanLHYLoc Address 0x8003_0078 Default 0x0000_0000 Definition Cursor Y Location register Bit Descriptions RSVD Reserved Unknown during read CLHEN Cursor Lower Half Enable Read Write Writing a 1 to this bit specif...

Page 254: ...ss 0x8003_0224 Default 0x0000_0000 Definition Blink Rate Control register Bit Descriptions RSVD Reserved Unknown during read EN Enable Read Write Writing a 1 to this bit enables hardware cursor blinking and enables the blink rate counter Writing a 0 to this bit disables hardware cursor blinking and disables the blink rate counter 0 Hardware cursor blinking not enabled 1 Hardware cursor blinking en...

Page 255: ... or CursorColor2 and CursorBlinkColor1 or CursorBlinkColor2 respectively An on off cursor blink cycle is controlled by the equation Blink Cycle 2 x 1 VCLK x HClkTotal Total x VLinesTotal Total x 255 RATE LUT Registers GrySclLUTR GrySclLUTG GrySclLUTB Address GrySclLUTR 0x8003_0080 through 0x8003_00FC GrySclLUTG 0x8003_0280 through 0x8003_02FC GrySclLUTB 0x8003_0300 through 0x8003_037C Default 0x00...

Page 256: ...on Read Write Writing a Vertical Counter Selection value to this bit selects which Vertical Counter is used for the current 3 bit pixel value 0 use FRAME_CNT3 1 use FRAME_CNT4 This bit is only defined for address locations GrySclLUTx Base 0x000 to GrySclLUTx Base 0x01C HORZ Horizontal Counter Selection Read Write Writing a Horizontal Counter Selection value to this bit selects which Horizontal Cou...

Page 257: ... X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01 001 X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01 010 X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01 011 X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01 100 X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01 101 X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 01 110 X...

Page 258: ...us Read Only When SWTCH 0 Switch Status 1 means that RAM0 is in the video pipeline and RAM1 is accessible to the bus When SWTCH 1 Switch Status 1 means that RAM1 is in the video pipeline and RAM0 is accessible to the bus During active video the switch does not occur until the beginning of the next frame When the video state machine is disabled the switch occurs almost immediately SWTCH Switch Read...

Page 259: ...en Blue Color Read Write Triple 8 bit Red Green and Blue Look Up Table LUT data is written to and read from these LUT locations The position in the LUT where the RGB data is read written is determined by the word address value ADR 9 2 When the LUT is in the video pipeline pixel data 23 0 is output from LUT word location ADR 9 2 Video Signature Registers VidSigRsltVal Address 0x8003_0200 Default 0x...

Page 260: ...ignature Control register Bit Descriptions EN Enable Read Write Writing a 1 to this bit enables the Linear Feedback Shift Register LFSR Writing a 0 to this bit disables the LFSR RSVD Reserved Unknown during read SPCLK Smart Panel Pixel Clock Read Write Writing a 1 to this bit enables the SPCLK output for calculation in the video signature Writing a 0 to this bit disables the SPCLK output for calcu...

Page 261: ...ables the HSYNC output for calculation in the video signature Writing a 0 to this bit disables the HSYNC output for calculation in the video signature VSYNC Vertical Synchronization Read Write Writing a 1 to this bit enables the VSYNC output for calculation in the video signature Writing a 0 to this bit disables the VSYNC output for calculation in the video signature PEN Pixel Bits Enable Read Wri...

Page 262: ...This indicates the start of the signature calculation for the Vertical frame VSIGEN is an internal block signal The SIG_ENABLE control to the video signature analyzer is enabled by the logical AND of VSIGEN and HSIGEN HSigStrtStop Address 0x8003_020C Default 0x0000_0000 Definition Horizontal Signature Bounds Start Stop register Bit Descriptions RSVD Reserved Unknown during read STOP Stop Read Writ...

Page 263: ...the Vertical frame VSIGCLR is an internal block signal The SIG_CLR control to the video signature analyzer is generated by the logical AND of VSIGCLR and HSIGCLR The SigClrStr control signal is also routed to an edge trigger capable interrupt on the interrupt controller for use as a programmable secondary raster engine interrupt output HCLR Horizontal Clear Read Write The HCLR value is the value o...

Page 265: ...ine Draw functions allow for solid lines or dashed lines The colors for line drawing can be either foreground color and background color or foreground color with the background being transparent The Graphics Accelerator also has an interrupt to indicate completion or termination due to error of the current function 8 2 Block Processing Modes The block transfer modes allow transferring blocks of da...

Page 266: ... to the destination The source data will not be modified unless the source is also the destination All pixel data is manipulated based on the value of the BLOCKMASK register and the desired operation The operations using C syntax of Logical Mask are AND This operator is used to remove pattern attributes from a pixel Dest BLOCKMASK Src OR This operator may be used to add regular pattern attributes ...

Page 267: ...in the BLOCKMASK register For unpacked 24 bpp fills the high byte is set to 0x00 8 2 4 Packed Memory Transfer A packed source means that all bits in a word are used for the source image The only exception is the last word which is not required to be used if the image size does not require the storage A packed source DOES NOT mean that all words are packed together The lines may have none or one or...

Page 268: ...priate angle The number of algorithm iterations is calculated based on the calculated pixel length of the line Pythagorean theorem A pattern up to 16 bits long repeats on an interval up to 16 bits In this mode visual correctness is emphasized over completeness For higher definition patterns details of the pattern may be lost Wide lines are not hardware accelerated but may be generated by stepping ...

Page 269: ...e stored in memory as 2 pixels per byte 8 4 3 Memory Organization for 8 Bits Per Pixel The 8 bpp storage format can be used to support 8 level grayscale and color displays For color displays this mode would use a software changeable palette in the Raster Engine to map 256 color selections to 24 bit colors Table 8 4 shows how 8 bpp images are stored in memory as 1 pixel per byte Table 8 2 bpp Memor...

Page 270: ...ignificant byte for each pixel would not be used for color information Table 8 5 shows how 16 bpp images are stored in memory as 1 pixel for every two bytes Table 8 4 8 bpp Memory Organization 31 24 23 16 15 8 7 0 0x0000 P 3 0 P 2 0 P 1 0 P 0 0 0x0004 P 7 0 P 6 0 P 5 0 P 4 0 0x0008 P 3 1 P 2 1 P 1 1 P 0 1 0x000C P 7 1 P 6 1 P 5 1 P 4 1 0x0010 P 3 2 P 2 2 P 1 2 P 0 2 0x0014 P 7 2 P 6 2 P 5 2 P 4 2 ...

Page 271: ... P 4 0 G P 4 0 B 0x0010 P 6 0 G P 6 0 B P 5 0 R P 5 0 G 0x0014 P 7 0 R P 7 0 G P 7 0 B P 6 0 R 0x0078 P 1 5 B P 0 5 R P 0 5 G P 0 5 B 0x007C P 2 5 G P 2 5 B P 1 5 R P 1 5 G 0x0080 P 3 5 R P 3 5 G P 3 5 B P 2 5 R 0x0084 P 5 5 B P 4 5 R P 4 5 G P 4 5 B 0x0088 P 6 5 G P 6 5 B P 5 5 R P 5 5 G 0x008C P 7 5 R P 7 5 G P 7 5 B P 6 5 R Table 8 7 24 bpp Unpacked Memory Organization 1 pixel 1 word 31 24 23 1...

Page 272: ...t be written with the number of 32 bit words minus 1 that are to be fetched from the SDRAM buffer If any pixel bit is in a word it must be counted as a full word 8 5 1 1 Example 8 BPP mode If a Block Copy starts at pixel 0 and 7 pixels are to be copied the BLKSRCWIDTH register would be loaded with a 0x1 2 words 1 word 0x1 since the 7th pixel resides in word 1 and the 0th pixel resides in word 0 Th...

Page 273: ...ext 4 words So the word width is 5 words 1 word 0x4 The pixels fetched are highlighted in Table 8 12 8 5 2 Pixel End and Start Two registers are used to control where in a word the first and last pixels reside This is required since in all color depths more than 1 pixel can reside in a word of memory This fact requires that the programmer provide the hardware with the exact information of where in...

Page 274: ...ginning bit position of 4 This makes 4 0x4 the value that is used for the SPEL field in the SRCPIXELSTRT register Let the starting SDRAM address of the destination image be 0x0020 Table 8 14 shows that Pixel 0 starts at bit 20 Pixel 1 starts at bit 16 etc The start pixel P0 is in the word at address 0x0020 and has a beginning bit position of 20 This makes 20 0x14 the value that is used for the SPE...

Page 275: ... at address 0x0034 and has a beginning bit position of 8 This makes 8 0x8 the value that is used for the EPEL field in the DESTPIXELSTRT register Note The word count for this example would be 2 1 1 words since P5 ends in the 2nd word So WIDTH 0x1 would be written to the BLKDESTWIDTH register 8 5 2 3 16 BPP WORD Layout For a Block Copy where 8 pixels are transferred per scan line let the starting S...

Page 276: ...let the starting SDRAM address of the source image be 0x0000 Table 8 19 shows that Pixel 1 starts at bit 24 The start pixel P1 is in the word at address 0x0000 and has a beginning bit position of 24 This makes 24 0x18 the value that is used for the SPEL field in the SRCPIXELSTRT register Let the starting SDRAM address of the destination image be 0x0058 Table 8 20 shows that Pixel 1 starts at bit 2...

Page 277: ...TRN register contains a 4 bit pattern Count CNT value and a 16 bit Pattern PTRN that defines 16 pixel on off patterns for line functions CNT specifies the position of the last bit used in the PTRN field starting at bit 0 of the PTRN field B For a solid line write CNT 0xF and PTRN 0xFFFF to the LINEPATTRN register The solid line will have the color value that is written to the MASK field in the BLO...

Page 278: ...ter See Pixel End and Start on page 8 9 for details 5 Setup BLKDESTSTRT Register Write the SDRAM address for the starting pixel of the 1st line to the ADR field in the BLKDESTSTRT register 6 Setup BACKGROUND Register If BG 1 in the BLOCKCTRL register write the desired background color value to the BG field in the BACKGROUND register if BG 0 in the BLOCKCTRL register the color value written to the ...

Page 279: ...rrupts are desired set the INTEN bit to 1 H Set the EN bit to 1 The final step is to wait for an interrupt or poll for EN 0 in the BLOCKCTRL register When the EN bit becomes cleared to 0 the line draw function is complete 8 6 2 Example of Breshenham s Algorithm Line Draw To achieve the following display and pattern follow Steps 1 to 14 in this section Display size is 640 x 480 x 16 bits per pixel ...

Page 280: ...01 abs 20 301 x 4095 81 281 x 4095 1180 409 which rounds to 1180 0x49C 9 Write WIDTH 0x50 to the BLKDESTWIDTH register where WIDTH abs X2 X1 4096 1 abs 20 101 4096 1 81 4096 1 81 1 80 0x50 10 Write HEIGHT 0x0 to the BLKDESTHEIGHT register where HEIGHT abs Y2 Y1 1 4096 abs 20 301 1 4096 281 1 4096 0 0686 0x0 11 Clear the BLOCKCTRL register by writing 0x0000_0000 to it 12 Write Line 1 DXDIR 0 DYDIR ...

Page 281: ... length is 640 divided by 4 160 0xA0 Usually the same LEN value is used in both the DESTLINELENGTH register and the SRCLINELENGTH register 4 Setup BLKDESTWIDTH Register Write the value of Stride minus 1 to the WIDTH field in the BLKDESTWIDTH register where WIDTH is determined by A Find how many pixels occupy a 32 bit word For example four 8 bit pixels can occupy a 32 bit word B Find the width of t...

Page 282: ...75 and the pixel depth is 16 bits the value for SPEL is 51 x 16 32 16 0x10 and the value for EPEL is 75 x 16 32 16 0x10 B Write the word aligned value of the SDRAM address for the beginning of the image that is to be copied to the BLKDESTSTRT register C Write the line length value to the LEN field in the SRCLINELENGTH register where LEN is determined by 1 Find how many pixels occupy a 32 bit word ...

Page 283: ...ELENGTH register where LEN is determined by 1 Find how many pixels occupy a 32 bit word For example four 8 bit pixels can occupy a 32 bit word 2 Find the width of the display in pixels For example a 640x480 display has a width of 640 pixels 3 The line length LEN is determined by the stride of the display that is how many 32 bit words are needed to populate the width of the display with pixels From...

Page 284: ...nabled to 1 This allows data from the source to be compared with the transparency pixel pattern to determine if the destination pixel is to be modified before it is written Without this bit enabled a direct block copy would occur The SYDIR SXDIR and DYDIR DXDIR direction bits must be configured These bits control the direction for the line accumulator Y and the word pixel counter X In a left to ri...

Page 285: ...SPEL 640 115 300 16 32 0 0x0 EPEL 640 115 20 300 20 16 32 0 0x0 E BLKDESTSTRT 640 115 300 2 147800 0x24158 F BLKDESTWIDTH 30 2 1 14 0xE G BLKDESTHEIGHT 20 H BLOCKCTRL Write 0x0000_0000 to the BLOCKCTRL register to clear it Write PACKD 0 to specify that the size of the source and destination images are the same Write P 0x4 to specify 16 bits pixel Write SXDIR 0 SYDIR 0 DXDIR 0 DYDIR 0 to specify th...

Page 286: ...LKSRCWIDTH No Read Write 12 bits Block Function Source Width Register 0x8004_0014 SRCLINELENGTH S RCLINELENGTH No Read Write 12 bits Block Source Line Length Register 0x8004_0018 BLKDESTWIDTH No Read Write 12 bits Block Function Destination Width Register 0x8004_001C BLKDESTHEIGHT No Read Write 11 bits Block Function Destination Height Register 0x8004_0020 DESTLINELENGTH No Read Write 12 bits Dest...

Page 287: ...ord For example if the beginning bit of a 16 bit pixel is located at bit 16 of a 32 bit word PEL 0x10 The PEL field and the ADR field in the BLKSRCSTRT register together define the starting pixel s address in the SDRAM frame buffer In REMAP mode the starting location written to the PEL field can be defined with bit level granularity For all other modes the granularity must be a multiple of the pix...

Page 288: ...ranularity must be a multiple of the pixel size in all video display modes For example acceptable values in 8 bpp mode are 0x00 0x08 0x10 and 0x18 SPEL Source Pixel Location Read Write For the starting pixel at the starting X Y coordinate of the 1st scan line of the destination image for a block copy the value in this field specifies where the beginning bit of the pixel is located in a 32 bit word...

Page 289: ...of the source image NA Not Assigned Not used returns written value BLKDESTSTRT Address 0x8004_000C Read Write Default 0x0000_0000 Mask 0xFFFF_FFFC Definition Block Destination Word Address Start register Bit Descriptions ADR Address Read Write The value in this field specifies the word address of the SDRAM frame buffer location that contains the starting pixel of the first scan line of the destina...

Page 290: ...in the 1st scan line of the source image For an example please refer to Table 8 18 on page 8 12 Six 32 bit words are needed to contain six 24 bit pixels So WIDTH 6 1 5 0x5 The maximum value for the field is 0xFFE 4095 words SRCLINELENGTH Address 0x8004_0014 Read Write Default 0x0000_0000 Mask 0x0000_0FFF Definition Block Source Line Length Register Bit Descriptions RSVD Reserved Unknown during rea...

Page 291: ...his example is 640 pixels divided by 4 where 4 is the number of 8 bit pixels that occupy a word So for this example LEN 640 4 160 0xA0 Usually the same LEN value is used in both the SRCLINELENGTH register and the DESTLINELENGTH register BLKDESTWIDTH Address 0x8004_0018 Read Write Default 0x0000_0000 Mask 0x0000_0FFF Definition Block Function Destination Width Register Bit Descriptions RSVD Reserve...

Page 292: ...t Descriptions RSVD Reserved Unknown during read HEIGHT Height Read Write For Block Fill or Block Copy functions the value in this field specifies the height in lines minus 1 of the destination image Since there is no BLKSRCHEIGHT register the source image must have the same height as the destination image For Line Draw functions the value in this field specifies the distance in lines minus 1 betw...

Page 293: ... occupy a 32 bit word For example four 8 bit pixels can occupy a 32 bit word 2 Find the width of the display in pixels For example a 640x480 display has a width of 640 pixels 3 The line length LEN is determined by the stride of the display that is how many 32 bit words are needed to populate the width of the display with pixels From steps 1 and 2 the stride for this example is 640 pixels divided b...

Page 294: ...at source information transfers are whole words with the possible exceptions of the beginning and ending words This allows images to be packed into any square configuration of whole words including a serial stream P Bits Per Pixel Read Write The value of this field as shown in Table 8 23 specifies the pixel mode depth that is used for Graphics Accelerator functions The Raster Engine has a similar ...

Page 295: ...etes Masking the interrupt by writing INTEN 0 and writing INTEOI 1 will halt the current Graphics Accelerator function BG Background Read Write When this bit is 0 during remap REMAP 0 source image pixels that have a value of 0 are unaffected transparent when they are copied to the destination image When this bit is 1 during remap REMAP 1 source image pixels that have a value of 0 are copied to the...

Page 296: ...re copied to the destination image with the color value in the MASK field of the BLOCKMASK register D Destination Mode Read Write The value in the this field specifies the destination mode 00 Disabled 01 Destination AND Mode 10 Destination OR Mode 11 Destination XOR Mode M Mask Mode Read Write The value in the this field specifies the mask mode 00 Disabled 01 Mask AND Mode 10 Mask OR Mode 11 Mask ...

Page 297: ...ead Write 0 Fill disabled 1 Fill with mask value enabled Reading this bit returns a valid value only when EN 1 TRANS Transparency Enable Read Write 0 Transparency disabled 1 Transparency enabled Reading this bit returns a valid value only when EN 1 INTEN Graphics Accelerator Interrupt Enable Read Write 0 Interrupt disabled 1 Interrupt enabled EN Initiate Graphics Acceleration Function Read Write R...

Page 298: ...The transparent pixel definition is located in the least significant BPP part of the field for modes less than 24 bpp Bits 0 23 are used for 24 bpp mode bits 0 15 are used for 16 bpp mode bits 0 7 are used for 8 bpp mode and bits 0 3 are used for 4 bpp mode BLOCKMASK Address 0x8004_002C Read Write Default 0x0000_0000 Mask 0x00FF_FFFF Definition Block Mask Register Bit Descriptions RSVD Reserved Un...

Page 299: ...r 16 bpp mode bits 0 7 are used for 8 bpp mode and bits 0 3 are used for 4 bpp mode BACKGROUND Address 0x8004_0030 Read Write Default 0x0000_0000 Mask 0x00FF_FFFF Definition Block Function Background Register Bit Descriptions RSVD Reserved Unknown during read BG Background Read Write When performing remap operations without transparency REMAP 1 and BG 1 in the BLOCKCTRL register the value in this ...

Page 300: ... maximum value is 4095 4096 and the minimum value is 1 4096 XINC X Increment Read Write The value in this field specifies a 12 bit binary fraction of a pixel to be accumulated in the horizontal X direction during a Line Draw function The maximum value is 4095 4096 and the minimum value is 1 4096 LINEINIT Address 0x8004_0038 Read Write Default 0x0000_0000 Mask 0x0FFF_0FFF Definition Line Draw Initi...

Page 301: ...hm The minimum fractional value is 1 4096 This field can also be initialized to account for truncation errors in the drawing algorithm LINEPATTRN Address 0x8004_003C Read Write Default 0x000F_FFFF Mask 0x000F_FFFF Definition Line Pattern Register Bit Descriptions RSVD Reserved Unknown during read CNT The value in this field specifies the pixel position in the PATRN field that defines the end of th...

Page 302: ...c Graphics Accelerator EP93xx User s Guide 88 8 If BG 1 in the BLOCKCTRL register a 0 causes a pixel fill from the BACKGROUND register If BG 0 in the BLOCKCTRL register a 0 is transparent When drawing solid lines write LINEPATTERN 0x000F_FFFF ...

Page 303: ...age One RAM is dedicated to the receiver and one dedicated to the transmitter These RAMs are mapped into the register space and are accessible via the AHB Figure 9 1 1 10 100 Mbps Ethernet LAN Controller Block Diagram 9 1 1 Detailed Description 9 1 1 1 Host Interface and Descriptor Processor The Host Interface can be functionally decomposed into the AHB Interface Controller and the Descriptor Proc...

Page 304: ...equests are prioritized over AHB read requests to allow faster back to back transfers 9 1 1 2 Reset and Initialization The Ethernet LAN Controller has three reset sources the AHB reset software reset from the SelfCtl register and individual channel resets via the BMCtl register The PHY is reset with the PHYRES function in compliance with the 802 3 specifications and has no effect on the MAC layer ...

Page 305: ... RAM while the MAC is operating will likely cause a malfunction There is no arbitration logic between direct AHB access and MAC Descriptor Processor access The MAC configurations registers and FIFO RAMs are only word accessible 9 1 2 MAC Engine The MAC engine is compliant with the requirements of ISO IEC 8802 3 1993 Sections 3 and 4 9 1 2 1 Data Encapsulation In transmission the MAC automatically ...

Page 306: ...t Fram e Packet Form at Type II only 1 byte up to 7 bytes 6 bytes 6 bytes optional field 2 bytes LLC data Pad FCS N bytes M bytes 4 bytes pre am ble fra m e length m in 64 bytes m ax 151 8 bytes alternating 1s 0s SFD DA SA S FD Start of Fram e Delim iter D A Destination Address S A Source Addre ss LLC Logical Link C ontrol FC S Fram e C heck S equence som etim es called C yclic R edu nd ancy C hec...

Page 307: ...til the medium no longer has a carrier 9 1 3 1 Carrier Deference Refer to Figure 9 4 Once sufficient bytes have been written to the transmit FIFO the MAC layer immediately moves to the Carrier Deference State Diagram The Carrier Deference state is independent of entry into the state diagram The MAC layer may enter the state diagram in any of its five states The MAC layer exits the Carrier Deferenc...

Page 308: ... has started The 2 part deferral has an advantage for AUI connections to either 10BASE 2 or 10BASE 5 If the deferral process simply allowed the IFG timer to complete then it is possible for a short Inter Frame Gap to be generated The 2 part deferral prevents short IFGs The disadvantage of the 2 part deferral is longer deferrals In 10BASE T systems either deferral method should operate about the sa...

Page 309: ...hm over the standard algorithm is that the modification reduces the possibility of multiple collisions on any transmission attempt The disadvantage is that the modification extends the maximum time needed to acquire access to the medium The host may choose to disable the back off algorithm altogether This is done through the control bit DisableBackoff TestCtl When set the MAC transmitter waits for...

Page 310: ...ncludes four programmable perfect address filters as well as the all ones filter for broadcast frames The RXCtl register is used to control whether a particular filter is used The filters themselves share the same address space and the value in the Address Filter Pointer register determines which filter is being accessed at any time The filters are arranged such that the first is the normal MAC ad...

Page 311: ...ter The filter output Hashed is used to determine if the received DA passed the hash filter When set the Hashed event bit shows that the received DA passed the hash filter When clear Hashed shows the failure of the DA to pass the hash filter Figure 9 6 CRC Logic Whenever the hashed filter is passed on good frames the output of the HR is presented on the Hash Table Index RStatQ A received good fram...

Page 312: ...nally passed on to the Host or discarded by the MAC Once the Flow Control Timer is set to a non zero value no new transmit frames are started until the count reaches zero The counter is decremented once every slot time while no frame is being transmitted 9 1 4 9 Transmit Flow Control When receive congestion is detected the driver may want to transmit a pause frame to the remote station to create t...

Page 313: ...a count is incremented such that the MSB is set the corresponding status bit in the Interrupt Status Register is set An interrupt is generated at this time if the corresponding enable bit is set in the Interrupt Enable Register Once the count is incremented to an all ones condition it will not be incremented further it will remain in this state until reset by a read operation 9 1 4 11 Accessing th...

Page 314: ... preamble for access to the PHY s registers 9 1 4 11 2 Steps for Writing To the PHY Registers 1 Read the value from SelfCtl register 2 Since most PHYs need a Preamble for the MAC to read write the PHY registers you may need to clear the PreambleSuppress bit 3 Ensure that the PHY is not busy by polling the MIIStatus_Busy bit in MIIStatus register 4 Put the PHY data into the PHY Data register 5 Issu...

Page 315: ... and avoiding some potential latency problems 9 2 2 Receive Descriptor Queue The receive descriptors are passed from the Host to the MAC via the receive descriptor queue The receive descriptor queue is a circular queue occupying a contiguous area of memory The location and size of the queue are set at initialization writing to the Receive Descriptor Queue Base Address Register the Receive descript...

Page 316: ...tors to the RXDEnq register The number is automatically added to the existing value When the MAC consumes descriptors by reading them into its on local storage internal MAC buffer the number read is subtracted from the total The Host can read the total number of unread valid descriptors left in the queue from the RXDEnq There is a restriction that no more than 255 descriptors may be added to the q...

Page 317: ...or a frame being continued from another buffer If there is not a frame to be continued that is start of a new frame the buffer will be discarded When a buffer is discarded in this manner there is no status posted BI Buffer Index The buffer index is provided for Host software purposes The MAC keeps an internal copy of the index and includes it with any status writes associated with a receive buffer...

Page 318: ...rnet may stop receiving frames The Current Address must be set to point to the first status entry to be used This would normally be the first entry same value as the base address When the receive status queue initialization is complete the Receive Status Enqueue register is used by the Host to pass free status locations to the MAC To simplify this process the Host writes the number of additional f...

Page 319: ...ta has been written to the data buffer not before The EOF and EOB bits in the status entry can be used to determine the cause of a status entry Receive Status queue Base Address 32 RxSBA Receive Status Queue bits 31 0 Receive Status Current Address 32 RxSCA Status 31 Buffer Index 15 RStatQ 0 RStatQ 1 RStatQ c c current frame Frame Length 16 RStatQ c 1 R S tatQ j Receive Status queue Base Length 16...

Page 320: ...of frame has been transferred The EOB is always set at this time to indicate that the MAC has finished transferring to the buffer The buffer is not necessarily full When a status event causes an interrupt the interrupt pin will be activated after the status has been transferred to the status queue 9 2 3 1 Receive Status Format Receive Status First Word Definition Receive Status first word Contains...

Page 321: ...for any receive frame for which the RX_ERR MII pin was activated OE Overrun Error The receive overrun bit is set on any frame which could not be completely transferred to system memory This could be as a result of insufficient buffer space or an excessive bus arbitration time FE Framing Error This bit is set for any frame not having an integral number of bytes and received with a bad CRC value Run...

Page 322: ...hed Individual Address 3 Receive Status Second Word Definition Receive Status second word Contains status information for the receiver operation Bit Descriptions RFP Receive Frame Processed The Receive Frame Processed bit is always written as a 1 by the MAC when the status is ready and it may be used by the Host to mark its progress through the status queue BI Buffer Index This field contains the ...

Page 323: ... 2 Receive Flow Figure 9 9 Receive Flow Diagram Device Driver Protocol Stack RECV Call 11 Receive Descriptor Queue 1 Receive Frame Data Receive Status Queue PCI Bus Receive Descriptor Registers RxDEQ Receive Descriptor Processor MAC Engine LAN Medium 2 3 4 7 5 8 9 12 10 Memory CS 8950 6 RxSEQ AHB System Memory ...

Page 324: ...to the protocol stack 11 Driver clears the Receive Frame Processed bit in Status Queue 12 Driver writes number of entries processed in the status queue freeing them for future use by the MAC 13 After the driver gets the used receive buffers back from the stack the driver may repeat step 2 Note Steps 1 11 and 13 are transparent to the MAC Steps 2 through 10 and 12 directly involve the MAC 9 2 3 3 R...

Page 325: ...ize Rx Descriptor and Status Queues Write RxDEQ and RxSEQ count Idle Load Descriptors Receive Frame 0 Receive Frame 1 Write RxDEQ with additional descriptor count Random timing between Write RxDEQ steps Receive Frame 2 Write Rx Status Process Rx Status write RxSEQ Load Descriptors Load Descriptors Write Rx Status Write Rx Status Process Rx Status write RxSEQ Process Rx Status write RxSEQ Write RxD...

Page 326: ...end of buffer 1 frame size larger than buffer size and status 4 for end of frame buffer The next two frames both occupy one data buffer each and one status each This could be the case for short frames that do not exceed the header size or the buffer size The result of this is that the status queue may be used at a different rate to the descriptor queue based on the type of traffic and the options ...

Page 327: ... Figure 9 12 Figure 9 12 Receive Frame Pre processing In c o m in g F ra m e D e s tin a t io n A d d re s s F ilte r P ro m is c u o u s A IA H a s h A M u l tic a s tA In d i vid u a lA B ro a d c a s tA F i lte r T a p s If th e f ilte r is n o t p a s s e d th e fra m e is d is c a rd e d F il te r P a s s e d A c c e p t A M a s k C R C R u n tA R u n tA A c c e p t M a s k s A c c e p t M a ...

Page 328: ...uld be an integral number of descriptors and must not exceed 64 Kbytes total The Transmit descriptor current address must also be set at initialization to point to the first descriptor to be used This would normally be the first entry same value as the base address Following initialization the MAC will start to use descriptors from the Current Descriptor Address wrapping back to the base pointer w...

Page 329: ...it Descriptor Format and Data Fragments Data Fragment 1 Fragment 1 Length inbytes number of bytes set in TxDesQLen Data Fragment 2 Fragment 2 Length inbytes Data Fragment n Fragment n Length in bytes Each Data Fragment may begin on any byte boundary and may endon any byte boundary E O F 1 Buffer Cmd 0 4 TxBufAdr 1 32 Buffer Index 1 15 Buffer Length 1 12 E O F 1 Buffer Cmd 1 4 TxBufAdr 2 32 Buffer ...

Page 330: ... end of frame The CMD field is 4 bits Only the AF bit is valid The other fields are reserved 9 2 3 9 Transmit Descriptor Format Transmit Descriptor Format First Word Definition Transmit Descriptor first word Contains the base address of the data buffer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TBA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBA register sizes are in bits and shown in parentheses T...

Page 331: ...ided to help the Host software keep track of the transmit buffers A copy of the index for the first buffer of a frame is kept in the MAC and is included in any status written for the particular frame AF Abort Frame When the Abort Frame and EOF bits are set in a descriptor the transmit frame will be terminated with a bad CRC A bad CRC is applied even when the InhibitCRC bit TXCtl is set The Abort F...

Page 332: ... queue it is a circular queue in contiguous memory space The location and size of the queue are set at initialization by the Host writing to the Transmit Status Queue Base Address and the Transmit Status Queue Base Length registers The base address must point to a word aligned memory location The length is set to the actual status queue length in bytes This should be an integral number of status e...

Page 333: ...tatus Queue Transmit Status Base Address TxSBA 32 register sizes are in bits and shown in parentheses 31 30 Buffer Index 15 bits 31 0 Status 0 Status 1 Status 2 Status m TxWE Transmitted Without Error TxFP Transmit Frame Processed Current Frame Status Next Status Position Transmit Status Current Address TxSCA 32 Frame Status 15 ...

Page 334: ...n a frame has been terminated by the Host with an Abort Frame command in the transmit descriptor the Frame Abort status bit is set LCRS Loss of CRS The Loss of CRS bit is set when a frame is transmitted and the MII CRS signal is not asserted at the end of preamble RSVD Reserved Unknown During Read OW Out of Window The Out of Window bit indicates that a collision was detected after the transmission...

Page 335: ...isions This field contains the number of collisions that were experienced in transmitting this frame TBI Transmit Buffer Index The transmit buffer index is a copy of the transmit buffer index from the first descriptor of a transmit frame This is provided as an aid to the Host software in keeping track of the transmit buffers ...

Page 336: ... 12 Transmit Flow Figure 9 16 Transmit Flow Diagram Device Driver Protocol Stack XMIT Call 1 TX_Complete Tx Descriptor Queue 2 Transmit Frame Data Tx Status Queue PCI Bus Transmit Descriptor Registers TxDEQ Transmit Descriptor Processor MAC Engine LAN Medium 3 4 5 6 7 8 9 11 10 Memory CS 8950 AHB System Memory ...

Page 337: ...rors and soft errors A hard error is generally considered a reliability problem This includes AHB bus access problems A soft error indicates that the frame was not successfully transmitted The error may be expected or rare A soft error needs a graceful recovery by the host driver Soft errors include excessive collisions SQE error if connected to a MAU Hard errors are parity errors if enabled syste...

Page 338: ...Descriptor and Status Queues Write TxDEQ with valid descriptor count Idle Read Tx Descriptors Send Frame 0 Send Frame 1 Write TxDEQ with valid descriptor count Write TxDEQ with valid descriptor count Random timing between Write TxEnq steps Send Frame 2 Write Tx Status Process Tx Status Read Tx Data Read Tx Descriptors Read Tx Descriptors Read Tx Data Read Tx Data Read Tx Data Write Tx Status Write...

Page 339: ...rdware initialization sequence for a driver 1 Determine what PHYs are available poll PHYs via the management interface via MICmd MIIData and MIISts registers 2 Enable auto negotiation to determine the mode of operation 10 100 Mbit FDX HDX This may be needed to determine the amount of buffering to use 3 Set RXDQBAdd and RXDCurAdd to point to the start of the receive descriptor queue 4 Set RXDQBLen ...

Page 340: ...ther processing 9 2 5 2 Receive Queue Processing 1 Read the RXStsQCurAdd This is the point to which the Host needs to process the status queue 2 Read status entries up to the value of RXStsQCurAdd 3 For each status entry process the receive data Set the respective status entry to 0 after the data has been processed 4 Write the number of statuses processed to the RXStsEnq 5 Write the number of desc...

Page 341: ...underrun occurs the Transmit Descriptor Processor will halt The underrun may be the result of insufficient bus bandwidth available or the lack of the next transmit descriptor The Host should perform the Transmit Restart Process detailed in Section 9 2 5 5 9 2 5 5 Transmit Restart Process Following a halt of the Transmit Descriptor Processor from a Halt on Underrun TxLength Error or setting the TxD...

Page 342: ...01_0050 0x8001_0055 IndAd MAC Individual Address Register shares address space with HashTbl 0x8001_0050 0x8001_0057 HashTbl MAC Hash Table Register shares address space with IndAd 0x8001_0060 GlIntSts MAC Global Interrupt Status Register 0x8001_0064 GlIntMsk MAC Global Interrupt Mask Register 0x8001_0068 GlIntROSts MAC Global Interrupt Read Only Status Register 0x8001_006C GlIntFrc MAC Global Inte...

Page 343: ...Length Register 0x8001_00C6 TXStsQCurL en MAC Transmit Status Queue Current Length Register 0x8001_00C8 TXStsQCurA dd MAC Transmit Status Queue Current Address Register 0x8001_00D0 RXBufThrshl d MAC Receive Buffer Threshold Register 0x8001_00D4 TXBufThrshl d MAC Transmit Buffer Threshold Register 0x8001_00D8 RXStsThrshl d MAC Receive Status Threshold Register 0x8001_00DC TXStsThrshld MAC Transmit ...

Page 344: ...0 implies RxFCE0 and IA1 implies RxFCE1 PauseA Pause Accept When set Pause frames are passed on to the Host as regular frames When clear the frames are discarded The handling of MAC Control frames depends on the Pause Accept bit as well as the appropriate Individual Accept and RxFlow Control Enable bits as follows Table 9 4 Individual Accept RxFlow Control Enable and Pause Accept Bits IA 1 0 Indiv...

Page 345: ... receiver When a frame is being received and SerRxON is cleared then that receive frame is completed No subsequent receive frames are allowed until SerRxON is set again RCRCA Runt CRC Accept When set received frames which pass the destination address filter but are smaller than 64 bytes and have a CRC error are accepted However the MAC discards any frame of length less than 8 bytes When clear fram...

Page 346: ...ividual Accept 0 When set received frames are accepted which the DA matches the Individual Address 0 Register Note It may become necessary for the host to change the destination address filter criteria and NOT go through a controller reset This can be done The host should 1 Clear SerRxON RXCtl to prevent an additional received frame while the filters are being changed 2 Modify the destination filt...

Page 347: ...n the transmit descriptor for a frame the frame will be terminated with a bad CRC TxPD Tx Pad Disable When this bit is set the MAC will not pad the frame to the legal minimum size 64 bytes If clear the MAC will pad the frame to the minimum legal frame size if the supplied length is less than 64 bytes The padded characters will be the last supplied character in the frame repeated OColl One Collisio...

Page 348: ...000 Definition Self Control Register Bit Descriptions RSVD Reserved Unknown During Read MDCDIV MDC Clock Divisor HCLK is divided by MDCDIV 1 to create the MDC clock frequency Default value is 0x07 which is divide by 8 Note Clause 22 2 2 1 in the IEEE 802 3 specification states that the maximum MDC clock rate is 2 5 MHz Most PHYs support clock rates faster than 2 5 MHz So modify the MDCDIV value ac...

Page 349: ...E pin is driven high and Remote Wake up Interrupt Status is set PDWE Power Down Wake up Enable Setting the Power Down Wake up Enable bit causes the MAC to enter the remote wake up mode when the AHB bus is powered down In this mode all receive frames that pass the destination address filter are scanned for the remote wake up pattern six bytes of FFh followed directly by sixteen consecutive copies o...

Page 350: ...nternal diagnostic locations which provide access to features not required for normal driver operation To access the internal registers the address of the register is written to the Diagnostic Address register and the Diagnostic Data register is used to access the actual data Bit Descriptions RSVD Reserved Unknown During Read ADDR Diagnostic Address The following table identifies the address map A...

Page 351: ...s access to the internal register pointed to by the value in the Diagnostic Address register For debug only Bit Descriptions DATA Internal register data value GT Address 0x8001_0040 Read Write Chip Reset 0x0000_0000 Soft Reset 0x0000_0000 Definition General Timer Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA 31 30 29 28 27 26 25 24 23 22 2...

Page 352: ...iodic time for the timer When the period is written the count is preloaded with the same value Setting a value of zero in the Period disables the generation of Timeout Status FCT Address 0x8001_0044 Read Write Chip Reset 0x0000_0000 Soft Reset 0x0000_0000 Definition Flow Control Timer Bit Descriptions RSVD Reserved Unknown During Read FCT Flow Control Timer value The Flow Control Timer is loaded a...

Page 353: ... The destination address must match one of first two individual addresses with the appropriate RxFlowControlEn bit set The Ethernet type field must match MAC Control Type The first two data bytes of the frame must equal 0x0001 When a transmit pause command is processed the MAC Control Type is inserted in the transmit frame as the ethernet type field TPT Transmit Pause Time When a transmit pause co...

Page 354: ... at offset 0x0050 through 0x005F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD AFP Table 9 5 Address Filter Pointer AFP Data Accessed at Offset 0050 through 005F 000 This is the primary Individual Address used in the recognition of Wake up frames as the source address for transmit pause frames and may be optionally used to qualify receive pause fra...

Page 355: ...lement destination address filters for receive frames The first two may also be used to qualify receive frames for flow control processing and the first address is used for wake up frame processing The fifth address pointer offset 0x110 is only used as the destination address for transmit pause frames The least significant byte of the Individual Address corresponds to the first byte of the address...

Page 356: ...rame passes the hash table test if the bit is a 0 the frame fails the hash table test The hash table may be used for either or both of individual addressed frames and group address frames depending on the IAHA and MA bits in RXCtl A frame has a group address if the first bit of the frame is a one If an individual address frame passes the hash test and the IAHA bit is set the frame passes the desti...

Page 357: ...total number of collisions experienced on the transmit interface including late collisions When the most significant bit of the count is set an optional interrupt may be generated The register is cleared automatically following a read and writing to the register will have no effect RXMissCnt Address 0x8001_0074 Read Only Chip Reset 0x0000_0000 Soft Reset 0x0000_0000 31 30 29 28 27 26 25 24 23 22 2...

Page 358: ...set an optional interrupt may be generated The register is cleared automatically following a read writing to the register will have no effect RXRuntCnt Address 0x8001_0078 Read Only Chip Reset 0x0000_0000 Soft Reset 0x0000_0000 Definition Receive Runt Count Register Bit Descriptions RSVD Reserved Unknown During Read RRC Receive Runt Count The receive runt count records the total number of runt fra...

Page 359: ... when set the transmitter ignores carrier sense for transmit deferral For normal loopback testing this bit should be set DB Disable backoff When set the backoff algorithm is disabled The MAC transmitter looks only for completion of the Inter Frame Gap before starting transmission When clear the backoff algorithm is used as described in Section 9 1 4 on page 9 7 IntEn 31 30 29 28 27 26 25 24 23 22 ...

Page 360: ...ll cause an interrupt to be generated when the last available receive descriptor has been read into the MAC RxSQIE Receive Status Queue Interrupt Enable When this bit is set an interrupt will be generated when the last available status queue entry has been written RXStsEnq 0 TxLEIE Transmit Length Error Interrupt Enable Setting this bit causes an interrupt to be generated when a transmit frame equ...

Page 361: ...Ov bit is set in the Interrupt Status Register If the RuntOviE bit is set at this time an interrupt is generated MIIIE MII Management Interrupt Enable When set the MII Interrupt enable causes an interrupt to be generated whenever a management read or write cycle is completed on the MII bus PHYSIE The PHY Status Interrupt Enable bit provides a mechanism to generate an interrupt whenever a change of...

Page 362: ...g a 1 to a location in this register clears the status bit writing a zero has no effect Reading the Interrupt Status Clear register clears all the bits in the register that are accessed as defined by the AHB HSIZE signal Therefore a routine which will handle all reported status may read via the Interrupt Status Clear thereby saving a write operation Bit Descriptions RSVD Reserved Unknown During Re...

Page 363: ...ore stops further transmit DMA transfers An excessively long frame is defined as one equal or longer than the value programmed in the Max Frame Length register The frame itself will be terminated with a bad CRC ECIE When set to 1 this bit indicates that the MAC has exhausted the transmit descriptor chain TxUHI This bit is set if the MAC runs out of data during a frame transmission and the Underrun...

Page 364: ... AHB cycle terminated abnormally The Queue ID bits Bus Master Status will indicate the DMA Queue which was active when the abort occurred DMA operation is halted on all queues until this bit is cleared and the queues are restarted via the Bus Master Control register OTHER This bit is set when a status other than that covered by bits 10 3 and 2 is present TxSQ This bit is set when a status affectin...

Page 365: ... condition occurs GlIntMsk Address 0x8001_0064 Read Write Chip Reset 0x0000_0000 Soft Reset 0x0000_0000 Definition Global Interrupt Mask Register This register is used to mask the GlIntSts bit to allow of block interrupts to the processor Bit Descriptions RSVD Reserved Unknown During Read INT Global interrupt mask bit When set any interrupt enabled by the Interrupt Enable Register will set the Glo...

Page 366: ...D Reserved Unknown During Read INT Global interrupt read only status bit This bit is set whenever the MACint signal to the interrupt controller is active GlIntFrc Address 0x8001_006C Write Only Chip Reset 0x0000_0000 Soft Reset 0x0000_0000 Definition Global Interrupt Force Register This register allows software to generate an interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 ...

Page 367: ...e set When the Busy bit is clear the write operation has been performed Read operations are performed by writing a read command to the MII Command register Opcode 10b PhyAd target phy RegAd source register which will also cause the Busy bit MII Status to be set When the read operation has been completed the Busy bit is cleared and the read data is available in the MII Data register MIICmd Address ...

Page 368: ... 0x0000_0000 Soft Reset 0x0000_0000 Definition MII Data Transfer Register Bit Descriptions RSVD Reserved Unknown During Read MIIData MII Data Register This register contains the 16 bit data word that is either written to or read from the appropriate PHY register MIISts Address 0x8001_0018 Read Only Chip Reset 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 ...

Page 369: ...en the operation has been completed Descriptor Processor Registers The Descriptor Processor Registers are in three parts the bus master control receive registers and transmit registers BMCtl Address 0x8001_0080 Read Write Chip Reset 0x0000_0000 Soft Reset 0x0000_0000 Definition Bus Master Control Register Bit Descriptions RSVD Reserved Unknown During Read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ...

Page 370: ...tatus from the internal FIFOs when a non zero threshold has been set UnH Underrun Halt When set this bit causes the transmit descriptor to perform the following operations when a transmit underrun is encountered 1 Halt all transmit DMA operations 2 Flush the transmit descriptor queue 3 Set transmit enqueue to zero This allows the host to re initialize the Transmit Descriptor Processor to start at ...

Page 371: ...Receive Header Length 1 in order to generate a status event EH1 Enable Header 1 When Enable Header1 is set a status is written to the receive status queue when the number of bytes specified in Receive Header Length1 have been transferred to the receive data buffer If the transfer either fills a receive buffer or ends a receive frame only an end of buffer or end of frame status is generated EEOB En...

Page 372: ...d When the initialization is complete the RxAct BMSts is set BMSts Address 0x8001_0084 Read Only Chip Reset 0x0000_0000 Soft Reset 0x0000_0000 Definition Bus Master Status Register Bit Descriptions RSVD Reserved Unknown During Read TxAct Transmit Active When this bit is set the channel is active and may be in the process of transferring transmit data Following a TxDisable Command Bus Master Contro...

Page 373: ...t data 010 Receive status 011 Transmit status 100 Receive descriptor 101 Transmit descriptor Descriptor Processor Receive Registers RXDQBAdd Address 0x8001_0090 Read Write Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Receive Descriptor Queue Base Address register The Receive Descriptor Queue Base Address defines the system memory address of the receive descriptor queue this address is us...

Page 374: ...y sets the number of receive descriptors that can be supplied to the MAC The length should be set at initialization time and must define an integral number of receive descriptors Bit Descriptions RSVD Reserved Unknown During Read RDBL Receive Descriptor Base Length RXDQCurLen Address 0x8001_0096 Read Write Note half word alignment Chip Reset 0x0000_0000 Soft Reset Unchanged 31 30 29 28 27 26 25 24...

Page 375: ...98 Read Write Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Receive Descriptor Current Address register The Receive Current Descriptor Address contains the pointer to the next entry to be read from the receive descriptor queue This should be set at initialization time to the required starting point in the descriptor queue During operation the MAC will update this address following success...

Page 376: ...ing Receive Descriptor Value Whenever complete descriptors are read by the MAC the Receive Descriptor Value is decremented by the number read For example if the Receive Descriptor Value is 0x07 and the Host writes 03 to the Receive Descriptor Increment the new Value will be 0x0A If the controller then reads two descriptors the Value will be 0x08 Bit Descriptions RSVD Reserved Unknown During Read R...

Page 377: ... Address 0x8001_00A0 Read Write Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Receive Status Queue Base Address The Receive Status Queue Base Address defines the system memory address of the receive status queue This address is used by the MAC to reload the Receive Current Status Address whenever the end of the status queue is reached The base address should be set at initialization time ...

Page 378: ...ceive status queue The length should be set at initialization time and must define an integral number of receive statuses Bit Descriptions RSVD Reserved Unknown During Read RSQBL Receive Status Queue Base Length RXStsQCurLen Address 0x8001_00A6 Read Write Note half word alignment Chip Reset 0x0000_0000 Soft Reset Unchanged 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 ...

Page 379: ...ead RSQCL Receive Status Queue Current Length RXStsQCurAdd Address 0x8001_00A8 Read Write Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Receive Status Queue Current Address The Receive Status Queue Base Address defines the system memory address of the receive status queue This address is used by the MAC to reload the Receive Status Queue Current Status Address whenever the end of the stat...

Page 380: ...alue Whenever complete statuses are written by the MAC the Receive Status Value is decremented by the number read For example if the Receive Status Value is 0x07 and the Host writes 0x03 to the Receive Status Increment the new Receive Status Value will be 0x0A If the controller then reads two descriptors the Value will be 0x08 Bit Descriptions RSVD Reserved Unknown During Read RSV Receive Status V...

Page 381: ...s will only be generated for header length 2 if the length is greater than that specified for header length 1 Bit Descriptions RSVD Reserved Unknown During Read RHL2 Receive Header Length 2 RHL1 Receive Header Length 1 Descriptor Processor Transmit Registers TXDQBAdd Address 0x8001_00B0 Read Write Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Transmit Descriptor Base Address register The ...

Page 382: ...criptor queue which thereby sets the maximum number of transmit descriptors that can be supplied to the MAC at any one time The length should be set at initialization time and must define an integral number of transmit descriptors Bit Descriptions RSVD Reserved Unknown During Read TDBL Transmit Descriptor Base Length TXDQCurLen Address 0x8001_00B6 Read Write Note half word alignment Chip Reset 0x0...

Page 383: ...0B8 Read Write Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Transmit Descriptor Queue Current Address register The Transmit Descriptor Queue Current Address contains the pointer to the next memory location to be read from the transmit descriptor queue This should be set at initialization time to the required starting point in the descriptor queue During operation the MAC will update this...

Page 384: ... Descriptor Value When complete descriptors are read by the MAC the Transmit Descriptor Value is decremented by the number read For example if the Transmit Descriptor Value is 0x07 and the Host writes 0x03 to the Transmit Descriptor Increment the new Value will be 0x0A If the controller then reads two descriptors the Value will be 0x08 Bit Descriptions RSVD Reserved Unknown During Read TDV Transmi...

Page 385: ...itialization time and must be set to a word aligned memory address Bit Descriptions TSQBA Transmit Status Queue Base Address TXStsQBLen Address 0x8001_00C4 Read Write Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Transmit Status Queue Base Length The Transmit Status Queue Base Length defines the actual number of bytes in the transmit status queue The length should be set at initialization...

Page 386: ...us Current Address and the end of the transmit status queue This value is used internally to wrap the pointer back to the start of the queue The register should not normally be written Bit Descriptions RSVD Reserved Unknown During Read TSQCL Transmit Status Queue Current Length TXStsQCurAdd Address 0x8001_00C8 Read Write Chip Reset 0x0000_0000 Soft Reset Unchanged 31 30 29 28 27 26 25 24 23 22 21 ...

Page 387: ...imit on the amount of receive data which is held in the receive data FIFO before a bus request will be scheduled When the number of words in the FIFO exceeds the threshold value the Descriptor Processor will schedule a bus request to transfer data The actual posting of the bus request may be delayed due to lack of resources in the MAC such as no active receive descriptor Note There are other reaso...

Page 388: ...eavily loaded TXBufThrshld Address 0x8001_00D4 Read Write Suggested Value 0020_0010 Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Transmit Buffer Threshold register The transmit buffer thresholds are used to set a limit on the amount of empty space allowed in the transmit FIFO before a bus request will be scheduled When the number of empty words in the FIFO exceeds the threshold value the...

Page 389: ...dress 0x8001_00D8 Read Write Suggested Value 0x0004_0002 Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Receive Status Threshold register The receive status threshold are used to set a limit on the amount of receive status which is held in the receive status FIFO before a bus request will be scheduled When the number of words in the FIFO exceeds the threshold value the Descriptor Processor...

Page 390: ...is more heavily loaded TXStsThrshld Address 0x8001_00DC Read Write Suggested Value 0x0004_0002 Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Transmit Status Threshold register The transmit status thresholds are used to set a limit on the amount of transmit status which is held in the transmit status FIFO before a bus request will be scheduled When the number of words in the FIFO exceeds t...

Page 391: ...00E0 Read Write Suggested Value 0x0004_0002 Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Receive Descriptor Threshold register The receive descriptor thresholds are used to set a limit on the amount of empty space allowed in the MAC s receive descriptor FIFO before a bus request will be scheduled When the number of empty words in the FIFO exceeds the threshold value the Descriptor Proces...

Page 392: ... Address 0x8001_00E4 Read Write Suggested Value 0x0004_0002 Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Transmit Descriptor Threshold register The transmit descriptor thresholds are used to set a limit on the amount of empty space allowed in the MAC s transmit descriptor FIFO before a bus request will be scheduled When the number of empty words in the FIFO exceeds the threshold value th...

Page 393: ... Read Write Chip Reset 0x0000_0000 Soft Reset Unchanged Definition Maximum Frame Length and Transmit Start Threshold register Bit Descriptions RSVD Reserved Unknown During Read MFL Maximum Frame Length The maximum frame length is a limit for the amount of data permitted to be transferred across the AHB bus for a transmit frame or on the wire for a receive frame When this limit is reached for a tra...

Page 394: ...hreshold The transmit start threshold defines the number of bytes that must be written to the transmit data FIFO before a frame will start transmission on the serial interface This value is primarily of concern when the transmit frame is spread across multiple descriptors and the first descriptors define small amounts of data ...

Page 395: ...nternal Peripheral On the EP93xx chip the following peripherals may be allocated to the 10 channels I2 S which contains 3 Tx and 3 Rx DMA Channels AAC which contains 3 Tx and 3 Rx DMA Channels UART1 which contains 1 Tx and 1 Rx DMA Channels UART2 which contains 1 Tx and 1 Rx DMA Channels UART3 which contains 1 Tx and 1 Rx DMA Channels IrDA which contains 1 Tx and 1 Rx DMA Channels Each peripheral ...

Page 396: ...e peripherals using the 10 internal M2P P2M DMA channels each with its own peripheral DMA bus capable of transferring data in both directions simultaneously The UART1 2 3 and IrDA can each use two DMA channels one for transmit and one for receive The AC 97 interface can use six DMA channels three transmit and three receive to allow different sample frequency data queues to be handled with low soft...

Page 397: ...grammed limit and also if the count was terminated by peripheral asserting DEOT Completion of transfer will cause a DMA interrupt on that channel and rollover to the other buffer descriptor if configured For byte or word wide peripherals the DMA will be programmed to request byte or word wide AHB transfers respectively The DMA will not issue an AHB HREQ for a transfer until it has sampled DREQ ass...

Page 398: ...nd 5 P2M channels support data transfers between Memory and Internal Peripherals which are byte wide Five dedicated channels are available to transfer data between internal peripheral and memory receive direction and five channels are available to transfer data between memory and peripheral transmit direction Transfers are controlled using a REQ ACK handshake protocol supported by each peripheral ...

Page 399: ...an 4 If the number of bytes is less than 4 then byte accesses are performed until the remainder of the data has been transferred If the peripheral ended the transfer with an error code an interrupt is generated and operation continues as normal using the next buffer descriptor if it has been set up to ensure that a minimal amount of data is lost The point at which the transfer failed can be determ...

Page 400: ...6 AHB Slave Interface Limitations The AHB slave interface is used to access all control and status registers The behavior of the AMBA AHB signals complies with the standard described in AMBA Specification Rev 2 0 from ARM Limited The DMA does not utilize the AHB slave split capabilities so does not receive HMASTER or HMASTERLOCK and does not drive HSPLIT It does not receive HPROT or HRESP and does...

Page 401: ... transmit peripheral DMA bus The transmit un packer contains 4 words one quad word of storage Additional latency is provided by FIFOs within the peripheral the size of which can be selected as appropriate for the peripheral The number of data transfers over the peripheral DMA bus that is the number of bytes are counted by packer un packer unit If the number of bytes transferred reaches the MaxTran...

Page 402: ...e and terminates the current memory buffer if there is a peripheral error TxEnd RxEnd indication while in the DMA_NEXT state and ABORT is active and ICE inactive No STALL interrupt is generated for this condition No data transfers occur in this state 10 1 9 1 3 DMA_ON The DMA Channel FSM enters this state when a base address is written in the stall state Data transfers occur in this state The DMA ...

Page 403: ...r The number of bytes transferred from a receive peripheral reaches MAXCNTx Note This refers to bytes entering the data packer and not just data transmitted over the AHB bus that is has same effect as RxEnd signal generated by the peripheral The DMA Controller asserts RxTC to the peripheral to indicate this condition The DMA will update the Channel Status Register generating a system interrupt whi...

Page 404: ...The DMA Control M2M FSM always enters the DMA_IDLE state when a channel is disabled CONTROL 3 The DMA Control M2M FSM exits the DMA_IDLE state and moves to the DMA_STALL state when the ENABLE bit of the CONTROL register is set 10 1 10 1 2 DMA_STALL The DMA M2M Control FSM enters the DMA_STALL state when an M2M channel is enabled No STALL interrupt is generated for this condition The DMA M2M Contro...

Page 405: ...ore the DMA_MEM_RD state is entered again The DMA M2M Control FSM enters the DMA_MEM_RD state on exit from the DMA_BWC_WAIT state if all the data present in the data bay had been transferred to memory when DMA_BWC_WAIT state was entered The DMA M2M Control FSM stays in this state until the data transfer from memory has completed for software trigger mode that is the data bay is filled with 16 byte...

Page 406: ... the FSM moves to the DMA_BUF_ON state and buffer1 becomes the active buffer available for a transfer 10 1 10 2 2 DMA_BUF_ON The DMA Buffer FSM enters the DMA_BUF_ON state from the DMA_NO_BUF state when one of the BCRx registers is written to The DMA Buffer FSM enters the DMA_BUF_ON state from the DMA_BUF_NEXT state when the transfer from the active buffer has ended This end of buffer can be due t...

Page 407: ...hing zero or due to receipt of a DEOT input from the external device when in external DMA transfer mode and DEOT is configured as an input signal to the DMA The TCS and EOTS status bits of the STATUS register indicate what caused the end of buffer Data transfers to from memory or external device can occur in the DMA_BUF_NEXT state When the DMA Buffer FSM transitions from DMA_BUF_NEXT to DMA_BUF_ON...

Page 408: ...he SAH bit correctly Source Address Hold so that on successive transfers from the peripheral the SAR_CURRENTx value will not increment thus reflecting the FIFO nature of the peripheral A channel receives a request from an external device and the transfer mode is set to be either memory to external device mode or external device to memory mode that is CONTROL TM 01 or 10 respectively The DMA drives...

Page 409: ... 4 Data Transfer Termination The DMA Controller terminates a memory to memory channel transfer under the following conditions For software triggered transfers which use a single buffer the transfer is terminated when the BCR register of the active buffer has reached zero The DONE status bit and corresponding interrupt if enabled are set In the case of double multiple buffer transfers termination o...

Page 410: ...s to allow access to another device peripheral CONTROL BWC register bits provide 12 levels of block transfer sizes If the BCR decrements to within 15 bytes of a multiple of the decode of BWC then the DMA bus request is negated until the bus cycle terminates to allow the AHB bus arbiter to switch masters If BWC is equal to zero then the bus request stays asserted until BCR zero that is the transfer...

Page 411: ...to the DMA_MEM_RD state to begin servicing the first request in cycle 4 4 The DREQ latch is reset as a result of this state change and 2 cycles later the DREQS status bit is cleared 5 A second request cannot be recognized until DREQS is cleared Hence the request received during cycle 2 is ignored by the DMA 6 A rising edge on DREQ during cycle 6 is latched and causes the DREQS status bit to be set...

Page 412: ...o the destination The maximum transfer count can be any arbitrary number of bytes The DMA Controller transfers data when it owns the AHB bus Note that with byte word quad word scheme that the DMA Controller employs it can never burst across a 1KB boundary The reason is that the DMA Controller only bursts when the 4 LSB Address bits are 0000b A 1 KB boundary has the LSB 10 Address bits being zero r...

Page 413: ... due to software introduced latency 10 1 12 3 M2M Channel Buffer Descriptors Only one M2M channel buffer descriptor is allocated per transaction There are two M2M buffer descriptors one for each of the 2 M2M channels Each buffer descriptor allows a channel double buffering scheme by containing programming for two buffers that is two source base addresses two destination base addresses and two buff...

Page 414: ...for each of 10 M2P memory to peripheral channels 5 Tx and 5 Rx plus the 2 M2M memory to memory channels Before programming a channel the clock for that channel must be turned on by setting the appropriate bit in the PwrCnt register of the Clock and State Controller block M2P Ch 7 M2P Ch 5 M2P Ch 8 M2P Ch 6 M2P Ch 9 M2P Ch 7 M2M Ch 0 M2P Ch 8 Lowest M2M Ch 1 M2P Ch 9 Table 10 3 DMA Memory Map ARM92...

Page 415: ...l Interrupt register 0x8000_03C4 0x8000_FFFC Not Used 0x8000_03C4 Table 10 4 Internal M2P P2M Channel Register Map Offset Register Name Access Bits Reset Value Channel Base Address 0x0000 CONTROL R W 6 0 Channel Base Address 0x0004 INTERRUPT R W TC 3 0 Channel Base Address 0x0008 PPALLOC R W 4 Channel dependant see register description Channel Base Address 0x000C STATUS RO 8 0 Channel Base Address...

Page 416: ...rupt NFBIntEn Setting this bit to 1 enables the generation of the NFB next frame buffer interrupt in the ON State of the DMA Channel State machine Setting this bit to zero disables generation of the NFB Interrupt Normally when the channel is enabled this bit should be 1 However in the case where the current buffer is the last then this bit can be cleared to prevent the generation of an interrupt w...

Page 417: ... to program a channels use on one of a number of different peripherals There can be 20 external peripherals 10 Tx and 10 Rx connected to the 20 ports of the DMA The 10 internal M2P DMA channels can serve 10 of these ports at one time Bit Descriptions RSVD Reserved Unknown During Read Note PPALLOC Table 10 5 Table 10 6 and Table 10 7 give the PPALLOC decode for the port allocation for both a transm...

Page 418: ...I2S3 Tx 0110 PORT 12 UART1 Tx 0111 PORT 14 UART2 Tx 1000 PORT 16 UART3 Tx 1001 PORT 18 IrDA Tx other values not used Table 10 6 PPALLOC Register Bits Decode for a Receive Channel Ch 1 3 5 7 9 PPALLOC 3 0 Port allocated Peripheral Allocated 0000 PORT 1 I2S1 Rx 0001 PORT 3 I2S2 Rx 0010 PORT 5 AAC1 Rx 0011 PORT 7 AAC2 Rx 0100 PORT 9 AAC3 Rx 0101 PORT 11 I2S3 Rx 0110 PORT 13 UART1 Rx 0111 PORT 15 UART...

Page 419: ...ver underflow condition will occur as soon as the peripheral s FIFO is full empty The interrupt is cleared by either disabling the channel or writing a new base address which will move the state machine onto the ON state NFBInt Indicates channel requires a new buffer This interrupt generated on a Channel State machine transition from NEXT to ON state if NFBIntEn set The interrupt is cleared by eit...

Page 420: ...G register if it is zero the channel was stopped by the DMA Channel if it is non zero the peripheral ended transfer with TxEnd RxEnd If the transfer ended with error ChError bit interrupt is set NFB A 1 indicates the Channel FSM has moved from NEXT State to ON State This means that the channel is currently transferring data from a DMA buffer but the next base address for the next buffer in the tra...

Page 421: ...t to 1 and transfers will occur using buffer0 If during this transfer BASE1 gets written to then NextBuffer gets set to 0 but the current transfer will continue using buffer0 until it terminates Then the DMA switches over to using buffer1 at which time the NFB interrupt is generated and software reads the NextBuffer status bit to determine what buffer descriptor is now free for update In this case...

Page 422: ...signed in the ON state because in this state the next buffer to be used is determined there is only one and this MAXCNT value is assigned to REMAIN The DMA State Machine counts down by one byte every time a byte is transferred between the DMA Controller and the Peripheral When this register reaches zero the current buffer transfer is complete and the TxTC RxTC are generated and used to indicate th...

Page 423: ...x Maximum byte count for the buffer BASEx Address BASE0 Channel Base Address 0x0024 Read Write BASE1 Channel Base Address 0x0034 Read Write Definition Base address for the current and next DMA transfer Bit Descriptions BASEx x 0 or 1 Base address for the current and next DMA transfer Loaded with start address after enabling the DMA Channel the latter event required to take the Channel State machin...

Page 424: ... for the channel registers for each of the 2 M2M channels that are shown in Table 10 8 the M2M Channel Register Map This mapping is common for each channel thus offset addresses are shown Note that M2M Channel 0 is dedicated to servicing External Device 0 and M2M Channel 1 is dedicated to servicing External Device 1 when in external DMA transfer mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 425: ...ion If SCT 1 then one word is read from the source memory location and copied to a block of memory the number of destination locations written to is determined by BCR If SCT 0 then the source address increments as normal after each successful transfer as determined by the transfer size this is the default setting In order to use this feature the SAR_BASEx and DAR_BASEx registers must contain word ...

Page 426: ...e triggered DMA capability A channel must be configured and enabled before setting the START bit This bit is not used for external DMA transfers or for IDE and SSP transfers For a double buffer software triggered DMA transfer the START bit need only be set once that is at the very beginning of transfer It is sufficient for software to program the other buffer descriptor only in order to guarantee ...

Page 427: ...request byte half word word wide AHB transfers depending on the width of the external device These bits are not used for software triggered M2M transfers 00 Byte 8 bits 01 Half word 16 bits 10 Word 32 bits 11 Not used For word accesses the lower 2 bits of the source destination address are ignored For half word accesses the lower bit of the source destination address is ignored Table 10 9 BWC Deco...

Page 428: ...Mode 00 Software initiated DMA transfer 01 Hardware initiated external DMA transfer that is transfer from memory to external device or to IDE or SSP 10 Hardware initiated external DMA transfer that is transfer from external device or IDE SSP to memory 11 Not used ETDP End of Transfer Terminal Count pin Direction Polarity 00 The DEOT TC pin is programmed as an active low end of transfer input 01 Th...

Page 429: ...use of a wait state counter that will mask hardware requests after each DMA write PWSC Peripheral Wait States Count Gives the latency in HCLK cycles needed by the peripheral to de assert its request line once the M2M transfer is finished During this latency period the DMA channel will not consider any request This wait state count is triggered after each peripheral width transfer right after the D...

Page 430: ... as determined by the transfer count external peripheral DEOT signal When a transfer completes software must clear the DONE bit before reprogramming the DMA by writing either a 0 or 1 to this bit This must be done even if the DMA interrupt is disabled The DMA will ignore any additional DREQs that it receives from the external peripheral if operating in external DMA mode until the software clears t...

Page 431: ... Reserved Unknown During Read Stall A 1 indicates channel is stalled and cannot currently transfer data because the START bit has not been programmed or an external device has not asserted DREQ When the channel is first enabled the Stall bit is suppressed until the first buffer has been transferred that is no stall interrupt generated when STALL state entered from IDLE state only when entered from...

Page 432: ...either 0 or 1 to this bit The DMA will ignore any more DREQs that it receives from the external device if operating in external peripheral mode until such time that software clears the DONE interrupt and reprograms the DMA with new BCRx values and this even if the DMA interrupt is disabled TCS Terminal Count status This status bit reflects whether or not the actual byte count has reached the progr...

Page 433: ... the double buffer pair Thus for a double buffer transfer both BCR registers must be programmed once before the NFB status bit can be used to determine when the next BCR register should be programmed 0 Not ready for next buffer update 1 Ready for next buffer updates NFB interrupt generated if not masked NB NextBuffer status bit Informs the NFB service routine after a NFB interrupt which pair of SA...

Page 434: ...e request is not validated yet the wait state counter is running 1 An external DMA request or a validated IDE SSP or external peripheral without handshaking request is pending DREQS can be polled by software at any time It can for example be used to determine whether or not the DMA needs to be set up for a transfer when the DMA is in the STALL state and is receiving DREQs but the BCRx registers ha...

Page 435: ...or a given block of data in a M2M transfer Only the lower 16 bits are valid Bit Descriptions RSVD Reserved Unknown During Read BCRx x 0 or 1 representing the double buffer per channel The BCR register must be loaded with the number of byte transfers to occur It decrements on the successful completion of the address transfer during the write to memory state of the M2M transfer At least 1 of the BCR...

Page 436: ...0x001C Read Write Definition This register contains the base memory address from which the DMA controller requests data Bit Descriptions SAR_BASEx x 0 or 1 representing the double buffer per channel This register contains the base memory address from which the DMA controller requests data At least 1 of the SAR_BASEx registers must be programmed before the ENABLE bit and the START bit in the case o...

Page 437: ...e trigger M2M mode are set in the Control register and also before the corresponding BCRx register is programmed The second buffer descriptor can be programmed while the transfer using the other buffer is being carried out thus reducing software latency impact When transferring from memory to external peripheral the DAR_BASEx will contain the base address of the memory mapped device SAR_CURRENTx A...

Page 438: ...NT1 Channel Base Address 0x003C Read Only Definition This is the Channel Current Destination Address Register Bit Descriptions DAR_CURRENTx Returns the current value of the channel destination address pointer Upon writing the BCRx register the contents of the DAR_BASEx register is loaded into the DAR_CURRENTx register and the x buffer becomes active Following completion of a transfer from a buffer...

Page 439: ...pts are clear the associated channel interrupt is clear Note The order of the internal M2P channel interrupts is for compatibility reasons with previous versions of software DMAChArb Address 0x8000_0380 Read Write Table 10 10 DMA Global Interrupt DMAGlInt Register Bit No Description D 31 12 RSVD D11 M2M Channel 1 Interrupt D10 M2M Channel 0 Interrupt D9 M2P Channel 8 Interrupt D8 M2P Channel 9 Int...

Page 440: ...tration Bit Descriptions RSVD Reserved Unknown During Read CHARB This bit controls DMA channel arbitration It is reset to 0 thus giving a default setting of internal Memory to Peripheral channels having a higher priority than Memory to Memory channels This bit can be set to 1 to reverse the default order that is giving M2M transfers a higher priority than internal M2P ...

Page 441: ...ace OpenHCI specification version 1 0a For additional information see Section P 3 in Chapter P Preface 11 1 1 Features The features of the USB Host Controller are Open Host Controller Interface Specification OpenHCI Rev 1 0 compliant Universal Serial Bus Specification Rev 2 0 compliant Support for both low speed and full speed USB devices Root Hub has three downstream ports Master and Slave AHB in...

Page 442: ...ata transfers used to communicate information from the USB device to the client software The Host Controller Driver polls the USB device by issuing tokens to the device at a periodic interval sufficient for the requirements of the device Isochronous Transfers Periodic data transfers with a constant data rate Data transfers are correlated in time between the sender and receiver Control Transfers No...

Page 443: ...gister set is a pointer to a location in shared memory named the Host Controller Communications Area HCCA The HCCA is the second communication channel The Host Controller is the master for all communication on this channel The HCCA contains the head pointers to the interrupt Endpoint Descriptor lists the head pointer to the done queue and status information associated with start of frame processin...

Page 444: ...re linked in a queue the first one queued is the first one processed Each data transfer type has its own linked list of Endpoint Descriptors to be processed Figure 11 3 Typical List Structure is a representation of the data structure relationships Figure 11 3 Typical List Structure The head pointers to the bulk and control Endpoint Descriptor lists are maintained within the operational registers i...

Page 445: ...nter array Figure 11 4 Interrupt Endpoint Descriptor Structure Figure 11 5 is a sample Interrupt Endpoint schedule The schedule shows one Endpoint Descriptors at a 1 ms poll interval two Endpoint Descriptors at a 2 ms poll interval one Endpoint at a 4 ms poll interval two Endpoint Descriptors at an 8 ms poll interval two Endpoint Descriptors at a 16 ms poll interval and two Endpoint Descriptors at...

Page 446: ...ishing the interrupt Endpoint Descriptor list head pointers in the HCCA The Host Controller Driver maintains the state of the HC list processing pointers list processing enables and interrupt enables 11 2 3 2 Bandwidth Allocation All access to the USB is scheduled by the Host Controller Driver The Host Controller Driver allocates a portion of the available bandwidth to each periodic endpoint If su...

Page 447: ...dpoint Descriptor to the tail of the appropriate list This may occur simultaneously with the Host Controller processing the list without requiring any lock mechanism Before dequeuing an Endpoint Descriptor the Host Controller Driver may disable the Host Controller from processing the entire Endpoint Descriptor list of the data type being removed to ensure that the Host Controller is not accessing ...

Page 448: ...nqueued by the Host Controller Driver For interrupt and isochronous transfers the Host Controller begins at the Interrupt Endpoint Descriptor head pointer for the current frame The list is traversed sequentially until one packet transfer from the first Transfer Descriptor of all interrupt and isochronous Endpoint Descriptors scheduled in the current frame is attempted For bulk and control transfer...

Page 449: ...ster includes a Data FIFO which will use a 44x37 bit Data FIFO 32 bit data 4 bit HCI_MBeN 3 0 byte lane enables and HCI_MWBstOnN burst on make up the width of the Data FIFO 11 2 5 3 HCI Slave Block This block contains the OHCI operational registers which are programmed by the Host Controller Driver HCD A H B H C I B U S AHB Slave AHB Master HCI Slave HCI Master USB State Control Data FIFO 64x8 Lis...

Page 450: ...plements The USB operational states of the Host Controller as defined in the OHCI Specification It generates SOF tokens every 1 ms It triggers the List Processor while HC is in the operational states 11 2 5 6 Data FIFO This block contains a 64x8 FIFO to store the data returned by endpoints on IN tokens and the data to be sent to the endpoints on OUT Tokens The FIFO is used as a buffer in case the ...

Page 451: ...mportant Before setting up any of the Host controller registers it is necessary to set the USH_EN bit bit 28 of the PwrCnt register Table 11 2 OpenHCI Register Addresses Address Register Name 0x8002_0000 HcRevision 0x8002_0004 HcControl 0x8002_0008 HcCommandStatus 0x8002_000C HcInterruptStatus 0x8002_0010 HcInterruptEnable 0x8002_0014 HcInterruptDisable 0x8002_0018 HcHCCA 0x8002_001C HcPeriodCurre...

Page 452: ...10 Definition Defines the revision of the OHCI specification with which this implementation is compatible Bit Description RSVD Reserved Unknown During Read REV This read only field contains the BCD representation of the version of the HCI specification that is implemented by this HC 0x10 Compatible with OHCI 1 0 HcControl Address 0x8002_0004 Default 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 ...

Page 453: ... of the periodic list does not occur after the next SOF HC must check this bit before it starts processing the list IE IsochronousEnable This bit is used by HCD to enable disable processing of isochronous EDs While processing the periodic list in a Frame HC checks the status of this bit when it finds an Isochronous ED F 1 If set enabled HC continues processing the EDs If cleared disabled HC halts ...

Page 454: ... the resume signaling from a downstream port HC enters USBSUSPEND after a software reset whereas it enters USBRESET after a hardware reset The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports 0 0 USBRESET 0 1 USBRESUME 1 0 USBOPERATIONAL 1 1 USBSUSPEND IR InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInt...

Page 455: ...ontroller commands Bit Descriptions RSVD Reserved Unknown During Read HCR HostControllerReset This bit is set by HCD to initiate a software reset of HC Regardless of the functional state of HC it moves to the USBSUSPEND state in which most of the operational registers are reset except those stated otherwise e g the InterruptRouting field of HcControl and no Host bus accesses are allowed This bit i...

Page 456: ...er it adds a TD to an ED in the Bulk list When HC begins to process the head of the Bulk list it checks BF As long as BulkListFilled is 0 HC will not start processing the Bulk list If BulkListFilled is 1 HC will start processing the Bulk list and will set BF to 0 If HC finds a TD on the list then HC will set BulkListFilled to 1 causing the Bulk list processing to continue If no TD is found on the ...

Page 457: ...it has been cleared HCD should only clear this bit after it has saved the content of HccaDoneHead SF StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber HC also generates a SOF token at the same time RD ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling It is the transition from no resume signaling t...

Page 458: ...ays generate a System Management Interrupt SMI immediately This bit is tied to 0b when the SMI pin is not implemented HcInterruptEnable Address 0x8002_0010 Default 0x0000_0000 Definition Enables interrupt sources Bit Descriptions RSVD Reserved Unknown During Read SO SchedulingOverrun Enable interrupt generation due to Scheduling Overrun WDH WritebackDoneHead Enable interrupt generation due to HcDo...

Page 459: ...its of this register This is used by HCD as a Master Interrupt Enable HcInterruptDisable Address 0x8002_0014 Default 0x0000_0000 Definition Disables interrupt sources Bit Descriptions RSVD Reserved Unknown During Read SO SchedulingOverrun Disable interrupt generation due to Scheduling Overrun WDH WritebackDoneHead Disable interrupt generation due to HcDoneHead Writeback SF StartofFrame Disable int...

Page 460: ...o this field disables interrupt generation due to events specified in the other bits of this register This field is set after a hardware or software reset HcHCCA Address 0x8002_0018 Default 0x0000_0000 Definition Base physical address of the Host Controller Communication Area Bit Description RSVD Reserved Unknown During Read AD HCCA Base physical address of the Host Controller Communication Area H...

Page 461: ... of this register is updated by HC after a periodic ED has been processed HCD may read the content in determining which ED is currently being processed at the time of reading HcControlHeadED Address 0x8002_0020 Default 0x0000_0000 Definition Physical address of the first endpoint descriptor of the control list Bit Description RSVD Reserved Unknown During Read AD ControlHeadED HC traverses the Cont...

Page 462: ...s the end of the Control list HC checks the ControlListFilled of HcCommandStatus If set it copies the content of HcControlHeadED to HcControlCurrentEDand clears the bit If not set it does nothing HCD is allowed to modify this register only when the ControlListEnable of HcControl is cleared When set HCD only reads the instantaneous value of this register Initially this is set to zero to indicate th...

Page 463: ...RSVD Reserved Unknown During Read AD BulkCurrentED This is advanced to the next ED after the HC has served the present one HC continues processing the list from where it left off in the last Frame When it reaches the end of the Bulk list HC checks the ControlListFilled of HcControl If set it copies the content of HcBulkHeadED to HcBulkCurrentED and clears the bit If it is not set it does nothing H...

Page 464: ...NextTD field of the TD HC then overwrites the content of HcDoneHead with the address of this TD This is set to zero whenever HC writes the content of this register to HCCA It also sets the WritebackDoneHead of HcInterruptStatus HcFmInterval Address 0x8002_0034 Default 0x0000_2EDF Definition Describes the bit time interval in a frame and the full speed maximum packet size Bit Descriptions 31 30 29 ...

Page 465: ...alue represents the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing scheduling overrun The field value is calculated by the HCD FIT FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval HcFmRemaining Address 0x8002_0038 Default 0x0000_0000 Definition Contains the time remaining in the...

Page 466: ...it Description RSVD Reserved Unknown During Read FN FrameNumber This is incremented when HcFmRemaining is re loaded It will be rolled over to 0x0 after 0xFFFF When entering the USBOPERATIONAL state this will be incremented automatically The content will be written to HCCA after HC has incremented the FrameNumber at each frame boundary and sent a SOF but before HC reads the first ED in that Frame A...

Page 467: ...ty over Control Bulk processing HC will therefore start processing the Interrupt list after completing the current Control or Bulk transaction that is in progress HcLSThreshold Address 0x8002_0044 Default 0x0000_0628 Definition Contains a value used by the host controller to determine whether to commit to the transfer of a maximum 8 byte LS packet before EOF Bit Description RSVD Reserved Unknown D...

Page 468: ...erSwitchingMode This bit is used to specify how the power switching of the Root Hub ports is controlled It is implementation specific This field is only valid if the NoPowerSwitching field is cleared 0 All ports are powered at the same time 1 Each port is powered individually This mode allows port power to be controlled by either the global switch or per port switching If the PortPowerControlMask ...

Page 469: ...reflect the same mode as PowerSwitchingMode This field is valid only if the NoOverCurrentProtection field is cleared 0 Over current status is reported collectively for all downstream ports 1 Over current status is reported on a per port basis NOCP NoOverCurrentProtection This bit describes how the overcurrent status for the Root Hub ports are reported When this bit is cleared the OverCurrentProtec...

Page 470: ...h bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set When set the port s power state is only affected by per port power control Set ClearPortPower When cleared the port is controlled by the global power switch Set ClearGlobalPower If the device is configured to global switching mode PowerSwitchingMode 0 this field is not valid bit 0 Reserved bit 1 ...

Page 471: ... This bit enables a ConnectStatusChange bit as a resume event causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt 0 ConnectStatusChange is not a remote wakeup event 1 ConnectStatusChange is a remote wakeup event WRITE SetRemoteWakeupEnable Writing a 1 sets DeviceRemoveWakeupEnable Writing a 0 has no effect LPSC READ LocalPowerStatusChange The Root Hub does n...

Page 472: ...rrentConnectStatus This bit reflects the current state of the downstream port 0 no device connected 1 device connected WRITE ClearPortEnable The HCD writes a 1 to this bit to clear the PortEnableStatus bit Writing a 0 has no effect The CurrentConnectStatus is not affected by any write Note This bit is always read 1 when the attached device is nonremovable DeviceRemoveable NDP 31 30 29 28 27 26 25 ...

Page 473: ... no effect If CurrentConnectStatus is cleared this write does not set PortEnableStatus but instead sets ConnectStatusChange This informs the driver that it attempted to enable a disconnected port PSS READ PortSuspendStatus This bit indicates the port is suspended or in the resume sequence It is set by a SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume ...

Page 474: ... reset signal is active WRITE SetPortReset The HCD sets the port reset signaling by writing a 1 to this bit Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortResetStatus but instead sets ConnectStatusChange This informs the driver that it attempted to reset a disconnected port PPS READ PortPowerStatus This bit reflects the port s power status regardless of th...

Page 475: ...f CurrentConnectStatus is cleared when a SetPortReset SetPortEnable or SetPortSuspend write occurs this bit is set to force the driver to re evaluate the connection status since these writes should not occur if the port is disconnected 0 no change in CurrentConnectStatus 1 change in CurrentConnectStatus Note If the DeviceRemovable NDP bit is set this bit is set only after a Root Hub reset to infor...

Page 476: ...is complete USBCfgCtrl Address 0x8002_0080 Read Write Default 0x0000_0000 Definition Used to implement some input signals to USB host controller for configuration through software Bit Descriptions RSVD Reserved Unknown During Read TPOC When asserted by software the corresponding port will enter DISCONNECT state These bits must be cleared before the ports can be reused TRCS Inverted internally and ...

Page 477: ...en asserted it indicates that currently host controller is accessing data buffer It is a status bit reporting to software and software does not need to take any action MSN Host controller new frame Software does not need to take any action because it is a status about a new frame that is generated RWU Host controller remote wakeup Software action when this bit is asserted is implementation specifi...

Page 479: ...mory types are SRAM ROM NOR FLASH External Peripheral that has an SRAM type interface Each memory bank can be configured to support Memory devices that have either 8 16 or 32 bit data paths For example Two 16 bit devices can be used in parallel to make a 32 bit data path Two 8 bit devices can be used in parallel to make a 16 bit data path One 16 bit device can be used standalone to make an 16 bit ...

Page 480: ...s respective memory space As shown in Figure 12 1 and Figure 12 3 the SMC captures read data on the HCLK edge that occurs just prior to the HCLK edge that de asserts the chip select output signal on the CSnX pin The output signal on the CSnX pin and the address outputs on the AD x pins are de asserted on the next HCLK edge The SMC can insert wait cycles into its access timing Wait cycles can be sp...

Page 481: ...er EP93xx User s Guide 1212 12 Figure 12 1 32 bit Read 32 bit Memory 0 Wait Cycles RBLE 1 WAITn Inactive Figure 12 2 32 bit Write 32 bit Memory 0 Wait Cycles RBLE 1 WAITn Inactive AD x DA x RDn OEn nCSx HCLK Data Read AD x DA x WRn and nDMQ 3 0 nCSx HCLK Data Write ...

Page 482: ...2 12 Figure 12 3 16 bit Read 16 bit Memory RBLE 1 WAITn Active Figure 12 4 16 bit Write 16 bit Memory RBLE 1 WAITn Active Address Data RDn OEn nCSx HCLK Data Read WAITn Delay due to WAITn synchronization AD x DA x WRn and nDMQ 1 0 nCSx HCLK Data Write WAITn Delay due to WAITn synchronization ...

Page 483: ...at it should accept write data only from the upper two bytes on the 32 bit bus and not accept data from the lower two bytes on the 32 bit bus In other words the upper two bytes in the 32 bit wide memory would be written and the lower two bytes would remain as they are unwritten Each memory bank can be specified to operate with either single read and write accesses or with burst of four page mode r...

Page 484: ...connect some PCMCIA card signals to the processor Other PCMCIA card signals also shown in Figure 12 5 connect directly to the processor IOWRn nPIOWR 1 MCREGn nPREG 1 MCELn nPC_CE1 1 MCEHn nPC_CE2 1 MCRESETn RESET_1 1 MCWAIT nWAIT 1 AD 10 8 PC_A 10 8 1 AD 7 0 PC_A 7 0 2 DA 15 0 PC_D 15 0 2 MCDIR PC_DIR 2 MCDAENn 2 MCADENn 2 VS2 GPIO F 7 VS2 2 READY GPIO F 6 PC_RDY 2 VS1 GPIO F 5 VS1 2 MCBVD2 GPIO F...

Page 485: ...D 2 1 nCF_VS 2 1 NCE_MCD 2 1 PCMCIA Connector PC_D 15 0 DA 15 0 MCDAENn MCDIR Address Buffer AD 7 0 MCWRn MCRDn MCWAIT MCELn MCREGn MCRESETn READY PC_A 7 0 NCE_WP NCE_READY Status Buffer GPIO PORT F 7 0 Processor Pins Data Transceiver PC_A 25 8 MCEHn nPC_CE1 nPC_CE2 nWAIT nPOE nPWE nPIORD IORDn nPIOWR IOWRn nPREG PC_RDY RESET_1 MCADENn AD 25 8 ...

Page 486: ...Table 12 6 and Table 12 7 respectively Note It is up to the programmer to provide an even address for all attribute memory access operations see PCMCIA Spec 2 1 because the PCMCIA controller will generate the physical address as shown in Table 12 6 and Table 12 7 regardless of whether the least significant address bit is 0b1 or 0b0 Note In Table 12 6 and Table 12 7 bit 1 and bit 0 of the address e...

Page 487: ...0 23 16 23 16 3 25 2 1 1 1 0 31 24 Invalid Byte 0 25 2 x 0 0 0 7 0 7 0 Byte 1 25 2 x 1 1 0 15 8 Invalid Byte 2 25 2 x 0 0 0 23 16 23 16 Byte 3 25 2 x 1 1 0 31 24 Invalid Table 12 7 Accesses to 16 Bit Attribute Common IO Memory Common IO Memory Access Attribute Memory Access Access Half Word IN Word Processor Address Bus AD 25 0 nPC_CE 2 nPC_CE 1 D15 D8 D7 D0 D15 D8 D7 D0 Word 2 transfers required ...

Page 488: ...sters below 0x8008_0000 SMCBCR 7 0 Bank Configuration Register 0 0x8008_0004 SMCBCR 7 0 Bank Configuration Register 1 0x8008_0008 SMCBCR 7 0 Bank Configuration Register 2 0x8008_000C SMCBCR 7 0 Bank Configuration Register 3 0x8008_0010 Reserved Reserved 0x8008_0014 Reserved Reserved 0x8008_0018 SMCBCR 7 0 Bank Configuration Register 6 0x8008_001C SMCBCR 7 0 Bank Configuration Register 7 0x8008_002...

Page 489: ...t of four accesses The number of wait cycles is specified by WST1 1 HCLKs For example if WST1 0x3 3 1 4 cycles of HCLK are inserted into the access timing On reset this field defaults to 0x1F slowest access to enable booting from ROM or FLASH memory device types RBLE Read Byte Lane Enable Read Write The value written to this bit specifies the output values on the DQMn 3 0 pins during a Read access...

Page 490: ...Writes to the memory device are allowed to occur or not occur 0 Yes SRAM FLASH 1 No ROM SRAM FLASH PME Page Mode Burst of 4 Enable Read Write 0 Page Mode is disabled non burst accesses occur 1 Page Mode is enabled Page Mode provides fast burst of four accesses where the A 3 and A 4 address bits are internally incremented 00 01 10 11 to access four sequential words This bit is reset to 0 MW Memory ...

Page 491: ...registers to control wait states and device width for attribute common memory and IO address spaces and a single PCMCIA control register to provide global control for the card PCAttribute Address 0x8008_0020 Read Write Default 0x0000_0000 Definition PC Card Attribute register Bit Descriptions RSVD Reserved Unknown During Read WA Attribute Space Width Read Write The value written to this bit specif...

Page 492: ... Attribute space setup time Read Write The value written to this field specifies the number of HCLK cycles minus 1 that the address strobe MCADENn is set up before assertion of the data strobe MCDAENn The Setup time is specified by PA 1 HCLK cycles For example if PA 0x25 the Setup time is 37 1 38 cycles of HCLK PCCommon Address 0x8008_0024 Read Write Default 0x0000_0000 Definition PC Card Common r...

Page 493: ...dress strobe MCADENn The Hold time is specified by HC 1 HCLK cycles For example if HC 0xC the Hold time is 12 1 13 cycles of HCLK PC Common space setup time Read Write The value written to this field specifies the number of HCLK cycles minus 1 that the address strobe MCADENn is set up before assertion of the data strobe MCDAENn The Setup time is specified by PC 1 HCLK cycles For example if PC 0x25...

Page 494: ...cles minus 1 between de asserting the data strobe MCDAENn and de asserting the address strobe MCADENn The Hold time is specified by HI 1 HCLK cycles For example if HI 0xC the Hold time is 12 1 13 cycles of HCLK PI IO space setup time Read Write The value written to this field specifies the number of HCLK cycles minus 1 that the address strobe MCADENn is set up before assertion of the data strobe M...

Page 495: ...s bit clears the Configuration Option register in the card This places the card into an unconfigured memory only interface state Writing a 0 to this bit allows normal PC Card operation WEN External Wait Enable Read Write Writing a 1 to this bit enables the MCWAIT input pin to be asserted by the card to insert wait cycles into the access timing Writing a 0 to this bit disables the MCWAIT input pin ...

Page 497: ...nfigured Special configuration bits for Synchronous ROM operation Ability to program Synchronous FLASH devices using write and erase commands Data is transferred between the controller and the synchronous memory device in quad word bursts Programmable for 16 or 32 bit data bus EP9307 EP9312 and EP9315 processors only SDRAM contents are preserved when a soft reset is asserted Power saving synchrono...

Page 498: ...g The CKE bit in the Global configuration register GlConfig is written to 1 to enable HCLK to be output on the SDCLK pin Initialize 1 MRS 1 and LCR 0 shown in Table are written to the GlConfig register to cause a NOP access to be issued Continuous NOP accesses are issued for 200 μs 3 Initialize 0 MRS 1 and LCR 0 are written to the GlConfig register to enable access to the Mode register that is ins...

Page 499: ... SDRAM device may be visible as four 4 Mbyte banks Table 13 3 shows address pin usage In Table 13 3 external pins are identified as AD 15 0 internal address signals are identified as A 27 1 The 2nd row of the table shows the address pins AD 15 0 that may be connected to the synchronous memory device depending on its address depth The remaining rows show how the device s linear address space is map...

Page 500: ...2 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 Column A27 A26 AP1 A25 A24 A8 A7 A6 A5 A4 A3 A2 A1 SDRAM 32 bit data Row and Bank A27 A26 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Column A27 A26 AP1 A25 A24 A9 A8 A7 A6 A5 A4 A3 A2 SFLASH 2K Page Mode 32 bit data Row and Bank A27 A26 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Column A27 A26 AP1 A25 A10 A9 A8 A7 A6 A5...

Page 501: ... in SDRAMDevCfg 3 0 space 10 Write the normal operating value to the Refcnt field in the RefrshTimr register To establish normal refresh operation 11 Write Initialize 0 MRS 1 and LCR 0 to the GlConfig register To allow the Mode register inside the SDRAM device to be accessed 12 Perform a read from each SDRAM in the SDRAMDevCfg 3 0 space The value of the address that is read defines the value that ...

Page 502: ...one specifies Interleaved AD 6 4 specifies CAS Latency CASL Only values of two or three are supported See Table 13 6 for CAS Latency values AD 8 7 specify Operation Mode OM This value must be zero for normal operation AD 9 specifies the Write Burst Mode WBM This value should be programmed to zero for devices that support burst such as SDRAM It should be set to zero for devices that do not support ...

Page 503: ...s 0xH001_8400 sets RAS 2 CAS 5 Sequential BL 4 Table 13 6 Sync Memory CAS CAS Value SDRAM SFLASH SROM 000 Reserved Reserved Reserved 001 Reserved 1 2 010 2 2 3 011 3 3 4 100 Reserved Reserved 5 101 Reserved Reserved 6 110 Reserved Reserved 7 111 Reserved Reserved 8 Table 13 7 Sync Memory RAS Burst Type and Write Burst Length Value SDRAM SFLASH SROM RAS 0 Not applicable Not applicable 1 clk RAS 1 N...

Page 504: ...N output driven low 4 Issue AUTO REFRESH command 5 Enter SELF REFRESH Mode 13 6 2 Exiting Self Refresh Mode When coming out of the Standby mode the following actions are carried out by the synchronous memory controller before the processor is started 1 Allow clock stabilization 2 SDCLKEN output driven high 3 Issue ten NOP accesses 4 Issue AUTO REFRESH accesses 5 Exit SELF REFRESH Mode 13 7 Program...

Page 505: ...her programming the Synchronous FLASH Configuration register before releasing the processor from reset or by using the contents of it s NonVolatileMODE register which must have been previously programmed 13 8 External Synchronous Memory System The synchronous memory system is decoded from the ARM Core s physical memory map into four independent address domains each having an address range of 256 M...

Page 506: ...controls the least significant byte lane the DQMn1 pin controls the next to least significant byte lane the DQMn2 pin controls the next to most significant byte lane and the DQMn3 pin controls the most significant byte lane The memory device uses the byte lane enable signals on the DQMn pins to determine which byte lane data it should accept during a Write operation For example if a 32 bit word is...

Page 507: ...ows the continuous address ranges used by a variety of different synchronous memory configurations Note that in the Continuous Address Range Per Segment column the value N can be 0x0 0xC 0xD 0xE or 0xF as shown in Table 13 12 Table 13 10 Memory Addressing Example Muxing Scheme B1 B0 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 16 Bits Data ROW BANK A27 A26 A22 A21 A20 ...

Page 508: ...0000 0xNC1F_FFFF 0xN000_0000 0xN01F_FFFF 0xN100_0000 0xN11F_FFFF 0xN400_0000 0xN41F_FFFF 128 Mbit 16 bit wide device 12 x 9 x 4 banks 16 Mbytes 0xN500_0000 0xN51F_FFFF 0xN800_0000 0xN81F_FFFF 0xN900_0000 0xN91F_FFFF 2 Mbytes 0xN000_0000 0xN07F_FFFF 0xN100_0000 0xN17F_FFFF 8 Mbytes 0xNC00_0000 0xNC1F_FFFF 0xND00_0000 0xND1F_FFFF 0xN000_0000 0xN03F_FFFF 0xN100_0000 0xN13F_FFFF 0xN400_0000 0xN43F_FFF...

Page 509: ...F 0xN800_0000 0xN83F_FFFF 0xN900_0000 0xN93F_FFFF 4 Mbytes 0xN300_0000 0xN37F_FFFF 0xN400_0000 0xN47F_FFFF 0xN500_0000 0xN57F_FFFF 8 Mbytes 0xNA00_0000 0xNA3F_FFFF 0xN600_0000 0xN67F_FFFF 0xNB00_0000 0xNB3F_FFFF 0xN700_0000 0xN77F_FFFF 0xNC00_0000 0xNC3F_FFFF 0xND00_0000 0xND3F_FFFF 0xNE00_0000 0xNE3F_FFFF 0xNF00_0000 0xNF3F_FFFF Table 13 11 EP93xx SDRAM Address Ranges 16 Bit Wide Data Systems Con...

Page 510: ...0000 0xN83F_FFFF 4 Mbytes 0xN000_0000 0xN0FF_FFFF 16 Mbytes 0xNC00_0000 0xNC3F_FFFF 0xN000_0000 0xN03F_FFFF 128 Mbit 32 bit wide device 12 x 8 x 4 banks 16 Mbytes 0xN400_0000 0xN43F_FFFF 0xN800_0000 0xN83F_FFFF 4 Mbytes 0xN000_0000 0xN0FF_FFFF 16 Mbytes 0xNC00_0000 0xNC3F_FFFF 0xN000_0000 0xN03F_FFFF 0xN100_0000 0xN13F_FFFF 0xN400_0000 0xN43F_FFFF 128 Mbit 2 x 16 bit wide device 12 x 9 x 4 banks 3...

Page 511: ...ystems Continued 256 Mbit 2 x 16 bit wide device 13 x 9 x 4 banks 64 Mbytes 0xN500_0000 0xN57F_FFFF 0xN800_0000 0xN87F_FFFF 0xN900_0000 0xN97F_FFFF 8 Mbytes 0xN000_0000 0xN1FF_FFFF 0xN400_0000 0xN5FF_FFFF 32 Mbytes 0xNC00_0000 0xNC7F_FFFF 0xND00_0000 0xND7F_FFFF 0xN000_0000 0xN07F_FFFF 0xN100_0000 0xN17F_FFFF 0xN200_0000 0xN27F_FFFF Table 13 11 EP93xx SDRAM Address Ranges 16 Bit Wide Data Systems ...

Page 512: ...de device 13 x 10 x 4 banks 128 Mbytes 0xN700_0000 0xN77F_FFFF 0xN800_0000 0xN87F_FFFF 0xN900_0000 0xN97F_FFFF 8 Mbytes 0xN000_0000 0xN7FF_FFFF 128 Mbytes 0xNA00_0000 0xNA7F_FFFF 0xNB00_0000 0xNB7F_FFFF 0xNC00_0000 0xNC7F_FFFF 0xND00_0000 0xND7F_FFFF 0xNE00_0000 0xNE7F_FFFF 0xNF00_0000 0xNF7F_FFFF Table 13 11 EP93xx SDRAM Address Ranges 16 Bit Wide Data Systems Continued Organization Device Size T...

Page 513: ...termine the state of the boot configuration pins Table 13 12 Address Bits Used for Chip Select Boot Option ASDO A31 A30 A29 A28 Chip select 1 0 0 0 0 nSDCS3 0 1 1 1 1 nSDCS3 X 1 1 1 0 nSDCS2 X 1 1 0 1 nSDCS1 X 1 1 0 0 nSDCS0 Table 13 13 Synchronous Memory Controller Registers Address Name Description 0x8006_0000 Reserved 0x8006_0004 GlConfig Global Configuration 0x8006_0008 RefrshTimr Refresh Time...

Page 514: ...has taken effect Bit Descriptions RSVD Reserved Unknown During Read CKE Synchronous memory Clock Enable Read Write Writing a value to this bit specifies if the enable signal that is output on the SDCLKEN is asserted or not 0 SDCLKEN is de asserted to save power only when there is no current access to any synchronous memory device 1 SDCLKEN is continuously asserted especially useful when booting fr...

Page 515: ...omplete before it allows burst accesses from another requester to begin LCR Load FLASH Command Register Read Write When Initialize 0 and MRS 1 writing a 1 to this bit allows commands to be issued to the Synchronous FLASH device as described in Programming Registers SyncFLASH Device on page 13 8 0 See Table 13 10 1 See Table 13 10 SMEMBust Synchronous Memory Busy Status Read Write This status bit s...

Page 516: ...Timr Address 0x8006_0008 Read Write Default 0x0000_0080 Table 13 14 Synchronous Memory Command Encoding Initialize MRS LCR Synchronous Memory Command 1 1 0 Issue NOP to Synchronous Memory 1 0 0 Issue PreALL Pre charge All to SDRAM 0 1 0 Enable access to Synchronous Memory device mode register 0 1 1 Issue command to Synchronous FLASH Memory devices 0 0 1 UNDEFINED Do not use 1 0 1 UNDEFINED Do not ...

Page 517: ...esh period but it must be written during the SDRAM initialization routine to the appropriate value for the SDRAM devices If this field is written to 0x0000 no refresh cycles are issued BootSts Address 0x8006_000C Read Only Default 0x0000_0000 Definition When power on reset is asserted the values of the boot mode option pins shown in Table 13 1 are latched The Boot Status register reflects those la...

Page 518: ...SyncROM or SyncFLASH Synchronous Memory Domain 3 nSDCS3 is re mapped to address 0x0000_0000 This re mapping of nSDCS3 does not change until after the boot process is completed and the processor is reset not power on reset At that time nSDCS3 is mapped back to address 0xF000_0000 the beginning address of Synchronous Memory Domain 3 SDRAMDevCfg 3 0 Address SDRAMDevCfg0 0x8006_0010 Read Write SDRAMDe...

Page 519: ...ctive synchronous memory device To assure correct programming results these registers should only be written when interrupts and DMA operations are disabled Bit Descriptions RSVD Reserved Unknown During Read AutoPrecharge SDRAM Automatic Precharge Read Write During SDRAM initialization the value written to this bit specifies if the Synchronous Memory controller should issue an automatic precharge ...

Page 520: ...nly use ARM assembly str instructions for Write accesses to SyncFLASH devices CasLat Synchronous memory CAS Latency Read Write The value written to this field specifies the CAS latency that the Synchronous Memory controller uses for Read or Write accesses to SDRAM or SyncROM devices 000 Reserved 001 CAS Latency 2 010 CAS Latency 3 also normal default 011 CAS Latency 4 100 CAS Latency 5 also defaul...

Page 521: ... Bus Width 0 If this bit is written to 1 the signals on the BA0 and BA1 pins are exchanged with the signals on the AD12 and AD13 pins respectively Only one of the SROM512 SROMLL and 2KPAGE bits can be 1 at any time With the exception of SROMLL these bits always operate in 32 bit memory bus width mode regardless of the setting of External Bus Width bit SROM512 Synchronous ROM 512 byte page Read Wri...

Page 522: ...S785UM1 Copyright 2007 Cirrus Logic SDRAM SyncROM and SyncFLASH Controller EP93xx User s Guide 1313 13 The value written to this bit specifies the width of the memory bus 0 Width is 32 bits 1 Width is 16 bits ...

Page 523: ...B interface The transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes The UART Includes a programmable baud rate generator which generates a common transmit and receive internal clock from the UART internal reference clock input UARTCLK Offers similar functionality to the industry standard 16C550 UA...

Page 524: ...system bus and provides an interface using memory mapped registers which are accessed under program control 14 2 1 2 DMA Block The DMA interface passes data between the UART FIFOs and an external DMA engine as an alternative to AMBA APB accesses See Chapter 10 DMA Controller on page 10 1 for additional details It may be configured to automatically move characters from the DMA engine to the transmi...

Page 525: ...14 3 Copyright 2007 Cirrus Logic UART1 With HDLC and Modem Control Signals EP93xx User s Guide 1414 14 Figure 14 1 UART Block Diagram AMBA AMBA APB Interface and Register Block and DMA Interface UARTRXD UARTTXD ...

Page 526: ...mit logic performs parallel to serial conversion on the data read from the transmit FIFO Control logic outputs the serial bit stream beginning with a start bit data bits least significant bit LSB first followed by parity bit and then stop bits according to the programmed configuration in control registers 14 2 1 8 Receive Logic The receive logic performs serial to parallel conversion on the receiv...

Page 527: ...t period and vice versa Data received or transmitted is stored in two 16 byte FIFOs though the receive FIFO has an extra three bits per character for status information For transmission data is written into the transmit FIFO This causes a data frame to start transmitting with the parameters indicated in UARTLCR Data continues to be transmitted until there is no data left in the transmit FIFO The B...

Page 528: ...IFOs In this case the transmit and receive sides of the UART have 1 byte holding registers the bottom entry of the FIFOs The overrun bit is set when a word has been received and the previous one was not yet read In this implementation the FIFOs are not physically disabled but the flags are manipulated to give the illusion of a 1 byte register 14 2 2 3 System diagnostic Loopback Testing It is possi...

Page 529: ... status lines nUARTCTS nUARTDCD and nUARTDSR change It is cleared by writing to the UART1IntIDIntClr register This interrupt is not independently connected to the system interrupt controller 14 2 3 2 UARTRXINTR The receive interrupt changes state when one of the following events occurs If the FIFOs are enabled and the receive FIFO is half or more full it contains eight or more words then the recei...

Page 530: ...unction of the individual masked sources This output is connected to the system interrupt controller to provide another level of masking on a individual peripheral basis The combined UART interrupt is asserted if any of the four individual interrupts above are asserted and enabled 14 3 Modem The modem hardware adds modem control signals RTSn DTRn and RI Two modem support registers provide a 16550 ...

Page 531: ...iddle of a transmitted bit and the value after this transition is the actual value of the bit That is a 0 bit is represented by a transition from high to low and a 1 bit by a transition from low to high Because a transition always occurs in the middle of a bit the receiver can always extract the proper data after a suitable period of synchronization provided the signal quality is good The third an...

Page 532: ... use an externally generated clock clear UART1HDLCCtrl CMAS but set UART1HDLCCtrl RXCM To force the transmitter to use the same external clock also set UART1HDLCCtrl TXCM The clock is either internal or external that is the receiver cannot use an external clock while the transmitter generates and sends an internal one Refer to the documentation for the DeviceCfg register in Syscon for the use and ...

Page 533: ...t sends the CRC if CRC is enabled and then sends from 1 to 16 closing flags as specified in the UART1HDLCCtrl FLAG field terminating the packet If TUS is one the transmitter aborts the packet In synchronous HDLC it sends a byte of all ones since seven consecutive ones signifies an abort following by at least one closing flag In asynchronous HDLC it sends an escape and then at least one closing fla...

Page 534: ...has overflowed the UART1HDLCSts RFL bit is set and the packet is discarded An interrupt is generated if the UART1HDLCCtrl RFLEN bit is also set 14 4 5 CRCs Several bits in the UART1HDLCCtrl determine how CRCs are generated by the transmitter and processed by the receiver By setting the CRCE bit the HDLC transmitter will calculate and append a CRC to each packet The CRC may be either 16 bit or 32 b...

Page 535: ... the abort is caused by a framing error a missing stop bit all bytes up to and including the misframed byte will appear in the receive FIFO Reading the last byte will also set the UART1HDLCSts FRE bit In synchronous mode if the abort is caused by a misaligned flag or a series of seven consecutive 1 s all bytes except the one containing the bit after the sixth 1 will appear in the receive FIFO If t...

Page 536: ...he UART1DMACtrl register is set and the HDLC receiver is in asynchronous mode if the receiver sees a break parity or framing error it will indicate an error condition via RxEnd on the DMA channel 14 4 9 Writing Configuration Registers It is assumed that various configuration registers for the UART HDLC are not written more than once in quick succession in order to insure proper synchronization of ...

Page 537: ...y of PCLK Table 14 4 UART1 Pin Functionality PIN Description RXD0 UART1 input pin TXD0 UART1 output pin CTSn Modem input Clear To Send DSRn Modem input Data Set Ready also used for DCDn Data Carrier Detect EGPIO 0 Modem input RIn Ring Indicator if Syscon register DeviceCfg 25 MODonGPIO is set Otherwise RIn is driven low DTRn Modem output Data Terminal Ready if Syscon register TESTCR 27 RTConGPIO i...

Page 538: ...n protocols of 115 200 baud 8 bit characters even parity one stop bit no space between characters There are 11 bits per character so 115 200 11 10 473 characters per second If both transmitting and receiving 20 945 characters per second pass through the UART Accessing the UART through the DMA interface requires one access per 32 bits implying only 20 945 4 5 236 AHB accesses per second Accessing t...

Page 539: ...IFO The write operation initiates transmission from the UART The data is prefixed with a start bit appended with the appropriate parity bit if parity is enabled and a stop bit The resultant word is then transmitted For received words if the FIFOs are enabled the data byte is extracted and a 3 bit status break frame and parity is pushed onto the 11 bit wide receive FIFO if the FIFOs are not enabled...

Page 540: ...ritten The data must be read in order to empty the FIFO BE Break Error This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full word transmission time defined as start data parity and stop bits This bit is cleared to 0 after a write to UART1RXSts In FIFO mode this error is associated with the character at the top of the FIFO...

Page 541: ...which is updated on a single write strobe generated by an UART1LinCtrlHigh write In order to internally update the contents of UART1LinCtrlMid or UART1LinCtrlLow a UART1LinCtrlHigh write must always be performed at the end To update the three registers there are two possible sequences UART1LinCtrlLow write UART1LinCtrlMid write and UART1LinCtrlHigh write UART1LinCtrlMid write UART1LinCtrlLow write...

Page 542: ...arity bits 0 Odd parity checking is performed which checks for an odd number of 1 s This bit has no effect when parity is disabled by Parity Enable bit 1 being cleared to 0 PEN Parity Enable 1 Parity checking and generation is enabled 0 Parity checking and generation is disabled and no parity bit is added to the data frame BRK Send Break 1 A low level is continually output on the UARTTXD output af...

Page 543: ...ad Write Default 0x0000_0000 Definition UART Line Control Register Low Bit Descriptions RSVD Reserved Unknown During Read BR Baud Rate Divisor bits 7 0 Least significant byte of baud rate divisor These bits are cleared to 0 on reset The baud rate divisor is calculated as follows Baud rate divisor BAUDDIV FUARTCLK 16 Baud rate 1 where FUARTCLK is the UART reference clock frequency A baud rate divis...

Page 544: ...nterrupt is enabled TIE Transmit Interrupt Enable If this bit is set to 1 the transmit interrupt is enabled RIE Receive Interrupt Enable If this bit is set to 1 the receive interrupt is enabled MSIE Modem Status Interrupt Enable If this bit is set to 1 the modem status interrupt is enabled UARTE UART Enable If this bit is set to 1 the UART is enabled Data transmission and reception occurs for UART...

Page 545: ...ART1LinCtrlHigh register If the FIFO is disabled this bit is set when the transmit holding register is full If the FIFO is enabled the TXFF bit is set when the transmit FIFO is full RXFE Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UART1LinCtrlHigh register If the FIFO is disabled this bit is set when the receive holding register is empty If the FIFO is ena...

Page 546: ... 1 if the UARTRTINTR receive timeout interrupt is asserted This bit is cleared when the receive FIFO is empty or the receive line goes active TIS Transmit Interrupt Status 1 The UARTTXINTR transmit interrupt is asserted which occurs when the transmit FIFO is not full 0 The transmit FIFO is full RIS Receive Interrupt Status 1 The UARTRXINTR receive interrupt is asserted which occurs when the receiv...

Page 547: ...tifies the DMA block when an error occurs Errors include break errors parity errors and framing errors TXDMAE TX DMA interface enable Setting to 1 enables the private DMA interface to the transmit FIFO RXDMAE RX DMA interface enable Setting to 1 enables the private DMA interface to the receive FIFO Modem Register Descriptions UART1ModemCtrl Address 0x808C_0100 Read Write 31 30 29 28 27 26 25 24 23...

Page 548: ... LBE bit to loopback the serial data When high modem control outputs RTSn and DTRn are forced high inactive and modem control inputs are driven by outputs DSR DTR CTS RTS RI2 OUT1 DCD OUT2 OUT2 OUT2 function Used for internal loopback OUT1 OUT1 function Used for internal loopback RTS RTS output signal 1 RTSn pin low 0 RTSn pin high DTR DTR output signal 1 DTRn pin low 0 DTRn pin high UART1ModemSts...

Page 549: ...DCDn pin changed state since last read TERI Trailing Edge Ring Indicator RI input pin has changed from low to high DDSR Delta DSR DSRn pin has changed state since last read DCTS Delta CTS CTSn pin has changed state since last read HDLC Register Descriptions UART1HDLCCtrl Address 0x808C_020C Read Write Default 0x0000_0000 Definition HDLC Control Register Bit Descriptions RSVD Reserved Unknown Durin...

Page 550: ...clear and synchronous HDLC is enabled TXENC Transmit Encoding method 1 Use Manchester bit encoding 0 Use NRZ bit encoding This bit has no effect unless synchronous HDLC is enabled RXENC Receive Encoding method 1 Use Manchester bit encoding 0 Use NRZ bit encoding This bit has no effect unless synchronous HDLC is enabled SYNC Synchronous Asynchronous HDLC Enable 0 Select asynchronous HDLC for TX and...

Page 551: ... at least 16 opening and closing flags The closing flags of one packet may also be the opening flags of the next one if the transmit line does not go idle in between Note that HDLC RX does not count flags only one is necessary or three in Manchester mode CRCN CRC polarity control 0 CRC transmitted not inverted 1 CRC transmitted inverted CRCApd CRC pass through 0 Do not pass received CRC to CPU 1 P...

Page 552: ...US Transmit FIFO Underrun Select 0 TX FIFO underrun causes CRC if enabled and stop flag to be transmitted 1 TX FIFO underrun causes abort escape flag to be transmitted CRCE CRC enable 0 No CRC is generated by TX or expected by RX 1 HDLC TX automatically generates and sends a CRC at the end of a packet and HDLC RX expects a CRC at the end of a packet CRCS CRC size 0 CRC CCITT 16 bits x16 x12 x5 1 1...

Page 553: ...ddMask Address 0x808C_0214 Read Write Default 0x0000_0000 Definition HDLC Address Mask Bit Descriptions AMSK Address mask value Supports 8 bit and 16 bit address masking If UART1HDLCCtrl AME 1 0 is 00b or 11b this register is not used UART1HDLCRXInfoBuf Address 0x808C_0218 Read Only Default 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AMSK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AMSK ...

Page 554: ...otal number of valid bytes read from the RX FIFO during the last HDLC frame BFRE Buffered Framing Error 0 No framing errors were encountered in the last frame 1 A framing error occurred during the last frame causing the remainder of the frame to be discarded BROR Buffered Receiver Over Run 0 The RX buffer did not overrun during the last frame 1 The receive FIFO did overrun during the last frame Th...

Page 555: ...not sense a carrier LNKIDL Link Idle Read Only 0 RX data signal has changed within two bit periods 1 RX data signal has not changed within two bit periods This bit is only valid when set up to receive Manchester encoded synchronous HDLC CRE CRC Error Read Only 0 No CRC check errors encountered in incoming frame 1 CRC calculated on the incoming data does not match CRC value contained within the rec...

Page 556: ...a 1 to this bit EOF End of Frame read only 0 Current frame has not been received completely 1 The data most recently read from the RX FIFO is the last byte of data within the frame Note This bit reflects the status associated with the last character read from the RX FIFO It changes with reads from the RX FIFO RFL Receive Frame Lost Read Write Set to 1 when an ROR occurred at the start of a new fra...

Page 557: ... request TAB Transmitted Frame Aborted Read Write Set 1 when a transmitted frame is terminated with an abort Cleared by writing to a 1 to this bit TFC Transmit Frame Complete Read Write Set to 1 whenever a transmitted frame completes whether terminated normally or aborted Cleared by writing to a 1 to this bit TFS Transmit FIFO Service request Read Only This bit is a copy of the TIS bit in the UART...

Page 559: ...cribed below 15 2 IrDA SIR Block The IrDA SIR block contains an IrDA SIR protocol Encoder decoder The SIR protocol Encoder decoder can be enabled for serial communication via signals nSIROUT and SIRIN to an infrared transducer instead of using the UART signals UARTTXD and UARTRXD If the SIR protocol Encoder decoder is enabled the UARTTXD line is held in the passive state HIGH and transitions of th...

Page 560: ...bit period In low power mode the transmit pulse width is specified as 3 16 of a 115 2 Kbps bit period This is implemented as three times the period of a nominal 1 8432 MHz clock IrLPBaud16 derived by dividing down the UARTCLK clock The frequency of IrLPBaud16 is set up by writing the appropriate divisor value to UARTILPR The active low encoder output is normally LOW for the marking state no light ...

Page 561: ...oto transistor base of the receiver pulling its output LOW This then drives the SIRIN signal LOW In low power IrDA mode the width of the transmitted infrared pulse is set to 3 times the period of the internally generated IrLPBaud16 signal 1 63 ns assuming a nominal 1 8432MHz frequency by changing the appropriate bit in UARTCR In both normal and low power IrDA modes during transmission the UART dat...

Page 562: ... bit to 1 in the control register UARTCR bit 7 and setting the SIRTEST bit to 1 in the test register UARTTMR bit 1 Data transmitted on nSIROUT will be received on the SIRIN input Note UART2TMR is the only occasion that a test register needs to be accessed during normal operation 15 2 3 IrDA Data Modulation The effect of IrDA 3 16 data modulation can be seen in Figure 15 2 Figure 15 2 IrDA Data Mod...

Page 563: ...ommodate the desired range of baud rates Fuartclk min 32 x baud_rate max Fuartclk max 32 x 65 536 x baud_rate min The frequency of UARTCLK must also be within the required error limits for all baud rates to be used To allow sufficient time to write the received data to the receive FIFO UARTCLK must be less than or equal to four times the frequency of PCLK Table 15 1 UART2 IrDA Modes Mode DeviceCfg...

Page 564: ...election number of stop bits and spacing between characters if receiving For example assume 115 200 baud 8 bit characters even parity one stop bit no space between characters There are 11 bits per character so 115 200 11 10473 characters per second If both transmitting and receiving 20 945 characters per second pass through the UART Accessing the UART through the DMA interface requires one access ...

Page 565: ... in the transmitter holding register the bottom word of the transmit FIFO The write operation initiates transmission from the UART The data is prefixed with a start bit appended with the appropriate parity bit if parity is enabled and a stop bit The resultant word is then transmitted For received words if the FIFOs are enabled the data byte is extracted and a 3 bit status break frame and parity is...

Page 566: ...empty the FIFO BE Break Error This bit is set to 1 if a break condition was detected indicating that the received data input was held LOW for longer than a full word transmission time defined as start data parity and stop bits This bit is cleared to 0 after a write to UART2RXSts In FIFO mode this error is associated with the character at the top of the FIFO When a break occurs only one 0 character...

Page 567: ...te strobe generated by an UART2LinCtrlHigh write So in order to internally update the contents of UART2LinCtrlMid or UART2LinCtrlLow a UART2LinCtrlHigh write must always be performed at the end To update the three registers there are two possible sequences UART2LinCtrlLow write UART2LinCtrlMid write and UART2LinCtrlHigh write UART2LinCtrlMid write UART2LinCtrlLow write and UART2LinCtrlHigh write T...

Page 568: ...y bits 0 Odd parity is performed this checks for an odd number of 1 s This bit has no effect when parity is disabled by Parity Enable bit 1 being cleared to 0 PEN Parity Enable 1 Parity checking and generation is enabled 0 Parity checking is disabled and no parity bit added to the data frame BRK Send Break 1 A low level is continually output on the UARTTXD output after completing transmission of t...

Page 569: ...x0000_0000 Definition UART Line Control Register Low Bit Descriptions RSVD Reserved Unknown During Read BR Baud Rate Divisor bits 7 0 Least significant byte of baud rate divisor These bits are cleared to 0 on reset The baud rate divisor is calculated as follows Baud rate divisor BAUDDIV FUARTCLK 16 Baud rate 1 where FUARTCLK is the UART reference clock frequency A baud rate divisor of zero is not ...

Page 570: ...essing the test registers during normal operation and SIRTEST must be cleared to 0 when loopback testing is finished This feature reduces the amount of external coupling required during system test 0 This bit is cleared to 0 on reset which disables the loopback mode RTIE Receive Timeout Enable If this bit is set to 1 the receive timeout interrupt is enabled TIE Transmit Interrupt Enable If this bi...

Page 571: ... and SIRIN UARTTXD remains in the marking state set to 1 Signal transitions on UARTRXD or modem status inputs will have no effect When the IrDA SIR encoder decoder is disabled nSIROUT remains cleared to 0 no light pulse generated and signal transitions on SIRIN will have no effect UARTE UART Enable If this bit is set to 1 the UART is enabled Data transmission and reception occurs for UART signals ...

Page 572: ...mpty If the FIFO is enabled the RXFE bit is set when the receive FIFO is empty BUSY UART Busy If this bit is set to 1 the UART is busy transmitting data This bit remains set until the complete byte including all the stop bits has been sent from the shift register This bit is set as soon as the transmit FIFO becomes non empty regardless of whether the UART is enabled or not DCD Data Carrier Detect ...

Page 573: ...us This bit is set to 1 if the transmit interrupt is asserted RIS Receive Interrupt Status This bit is set to 1 if the receive interrupt is asserted MIS Modem Interrupt Status This bit is set to 1 if the modem status interrupt is asserted UART2IrLowPwrCntr Address 0x808D_0020 Read Write Default 0x0000_0000 Definition UART IrDA Low Power Divisor Register This is an 8 bit read write register that st...

Page 574: ...a zero value will result in no IrLPBaud16 pulses being generated UART2DMACtrl Address 0x808D_0028 Read Write Default 0x0000_0000 Definition UART DMA Control Register Bit Descriptions RSVD Reserved Unknown During Read DMAERR RX DMA error handing enable If 0 the RX DMA interface ignores error conditions in the UART receive section If 1 the DMA interface stops and notifies the DMA block when an error...

Page 575: ...s the receive data path during IrDA transmission testing requires SIR to be configured in full duplex mode This bit must be set to 1 to enable SIR system loopback testing when the normal mode control register UART2Ctrl bit 7 Loop Back Enable LBE has been set to 1 Clearing this bit to 0 disabled the receive logic when the SIR is transmitting normal operation This bit defaults to 0 for normal half d...

Page 577: ...2 signals in the MCR register define the TENn operating mode TENn can be configured to assert whenever the UART transmit buffer has data to send or to operate under software control For additional details about UART1 refer to Chapter 14 UART1 With HDLC and Modem Control Signals on page 14 1 16 2 Implementation Details 16 2 1 UART3 Package Dependency UART3 uses package pins RXD2 TXD2 and EGPIO 3 Se...

Page 578: ... Accessing the UART via the APB this requires APB AHB bus bandwidth Then both a read and write are required for each 8 bit data byte Bandwidth requirements also depend on the selected baud rate character size parity selection number of stop bits and spacing between characters if receiving For example assume 115 200 baud 8 bit characters even parity one stop bit no space between characters There ar...

Page 579: ...ess 0x808E_0000 Read Write Default 0x0000_0000 Definition UART3 Data Register Bit Descriptions RSVD Reserved Unknown During Read DATA UART Data read for receive data write for transmit data For words to be transmitted if the FIFOs are enabled data written to this location is pushed onto the transmit FIFO if the FIFOs are not enabled data is stored in the transmitter holding register the bottom wor...

Page 580: ...ad Write Default 0x0000_0000 Definition UART3 Receive Status Register and Error Clear Register Provides receive status of the data value last read from the UART3Data A write to this register clears the framing parity break and overrun errors The data value is not important Bit Descriptions RSVD Reserved Unknown During Read OE Overrun Error 1 when data is received and the FIFO is already full 0 Cle...

Page 581: ...3RXSts In FIFO mode this error is associated with the character at the top of the FIFO FE Framing Error When this bit is set to 1 it indicates that the received character did not have a valid stop bit a valid stop bit is 1 This bit is cleared to 0 by a write to UART3RXSts In FIFO mode this error is associated with the character at the top of the FIFO UART3LinCtrlHigh Address 0x808E_0008 Read Write...

Page 582: ...e logic does not check for two stop bits being received EPS Even Parity Select 1 Even parity generation and checking is performed during transmission and reception which checks for an even number of 1s in data and parity bits 0 Odd parity generation and checking is performed during transmission and reception which checks for an odd number of 1s This bit has no effect when parity is disabled by Par...

Page 583: ...ud Rate Divisor bits 15 8 Most significant byte of baud rate divisor These bits are cleared to 0 on reset UART3LinCtrlLow Address 0x808E_0010 Read Write Default 0x0000_0000 Definition UART3 Line Control Register Low Bit Descriptions RSVD Reserved Unknown During Read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD BR 31 30 29 28 27 26 25 24 23 22 21 2...

Page 584: ...During Read LBE Loopback Enable If this bit is set to 1 data sent to TXD is received on RXD This bit is cleared to 0 on reset which disables the loopback mode RTIE Receive Timeout Enable If this bit is set to 1 the receive timeout interrupt is enabled TIE Transmit Interrupt Enable If this bit is set to 1 the transmit interrupt is enabled RIE Receive Interrupt Enable If this bit is set to 1 the rec...

Page 585: ... the FIFO is disabled this bit is set when the receive holding register is full If the FIFO is enabled the RXFF bit is set when the receive FIFO is full TXFF Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UART3LinCtrlHigh register If the FIFO is disabled this bit is set when the transmit holding register is full If the FIFO is enabled the TXFF bit is set when...

Page 586: ...tus input That is the bit is 1 when the modem status input is 0 CTS Clear To Send status This bit is the complement of the UART clear to send nUARTCTS modem status input That is the bit is 1 when the modem status input is 0 UART3IntIDIntClr Address 0x808E_001C Read Write Default 0x0000_0000 Definition UART3 Interrupt Identification and Interrupt Clear Register Interrupt status is read from UART3In...

Page 587: ...receive FIFIO is empty MIS Modem Interrupt Status This bit is set to 1 if the UARTMSINTR modem status interrupt is asserted This bit is cleared by writing any value to this register UART3LowPwrCntr Address 0x808E_0020 Read Write Default 0x0000_0000 Definition UART3 IrDA Low Power Divisor Register This register is present in UART3 but is not supported Bit Descriptions RSVD Reserved Unknown During R...

Page 588: ...FIFO RXDMAE RX DMA interface enable Setting to 1 enables the private DMA interface to the receive FIFO UART3ModemCtrl Address 0x808E_0100 Read Write Default 0x0000_0000 Definition Modem Control Register Only the OUT1 and OUT2 bits have functionality in UART3 The RTS and DTR bits exist but have no function Bit Descriptions RSVD Reserved Unknown During Read OUT2 OUT2 function Controls the TENn outpu...

Page 589: ...onous HDLC mode using NRZ encoding 0 Do not generate clock This bit has no effect unless TXENC is clear and synchronous HDLC is enabled RXCM Receive Clock Mode 1 Use external 1x clock when in synchronous HDLC mode using NRZ encoding 0 Do not use external clock This bit has no effect unless RXENC is clear and synchronous HDLC is enabled TXENC Transmit Encoding method 1 Use Manchester bit encoding 0...

Page 590: ...set RILEN Receive Information Lost Interrupt Enable 0 RIL interrupt will not occur 1 RIL interrupt will occur whenever RIL bit is set RFLEN Receive Frame Lost Interrupt Enable 0 RFL interrupt will not occur 1 RFL interrupt will occur whenever RFL bit is set RTOEN Receiver Time Out Interrupt Enable 0 RTO interrupt will not occur 1 RTO interrupt will occur whenever RTO bit is set FLAG Minimum number...

Page 591: ...g 11 Undefined no matching RXE HDLC Receive Enable 0 Disable HDLC RX If UART is still enabled UART may still receive normally 1 Enable HDLC RX TXE HDLC Transmit Enable 0 Disable HDLC TX If UART is still enabled UART may still transmit normally 1 Enable HDLC TX TUS Transmit FIFO Underrun Select 0 TX FIFO underrun causes CRC if enabled and stop flag to be transmitted 1 TX FIFO underrun causes abort ...

Page 592: ...If UART3HDLCCtrl AME is 00 or 11 this register is not used UART3HDLCAddMask Address 0x808E_0214 Read Write Default 0x0000_0000 Definition HDLC Address Mask Bit Descriptions AMSK Address mask value Supports 8 bit and 16 bit address masking If UART3HDLCCtrl AME is 00 or 11 this register is not used 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AMV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AMV 31 30 29...

Page 593: ...ring the last HDLC frame BFRE Buffered Framing Error 0 No framing errors were encountered in the last frame 1 A framing error occurred during the last frame causing the remainder of the frame to be discarded BROR Buffered Receiver Over Run 0 The RX buffer did not overrun during the last frame 1 The receive FIFO did overrun during the last frame The remainder of the frame was discarded BCRE Buffere...

Page 594: ... the RX FIFO It changes with reads from the RX FIFO ROR Receive FIFO Overrun Read Only 0 RX FIFO has not overrun 1 RX logic attempted to place data in the RX FIFO while it was full The most recently read data is the last valid data before the overrun The rest of the incoming frame is dropped EOF is also set Note This bit reflects the status associated with the last character read from the RX FIFO ...

Page 595: ... FIFO It changes with reads from the RX FIFO RFL Receive Frame Lost Read Write Set to 1 when an ROR occurred at the start of a new frame before any data for the frame could be put into the RX FIFO Cleared by writing a 1 to this bit RIL Receive Information buffer Lost Read Write Set to 1 when the last data for a frame is read from the RX FIFO and the UART1HDLCRXInfoBuf has not been read since the l...

Page 596: ...o this bit TFC Transmit Frame Complete Read Write Set to 1 whenever a transmitted frame completes whether terminated normally or aborted Cleared by writing to a 1 to this bit TFS Transmit FIFO Service request Read Only This bit is a copy of the TIS bit in the UART interrupt identification register 0 TX FIFO is full or TX disabled 1 TX FIFO not full and TX enabled May generate an interrupt and sign...

Page 597: ...Infrared FIR Transmission reception rate is 4 Mb s 17 2 IrDA Interfaces The Infrared Interface Module implements in hardware the physical layer of an infrared serial port compliant with version 1 1 of the IrDA standard Communication speeds of up to 4 Mbit sec are supported When combined with analog transducer components it provides a complete interface between infrared media and an AMBA compliant ...

Page 598: ...bit rate of 4 Mbit s Modulation demodulation is by a phase shift key scheme called pulse position modulation 4 PPM One of four signalling symbols represent each possible pair of data bits Data encoding uses a packet format that prefixes bit and symbol synchronization flags to data and appends a 32 bit CRC and stop flag to the end of each packet The start and stop flags use signalling symbols that ...

Page 599: ...follows MIR Clear BRD bit in IrControl IrCon for 0 576 Mbit sec Set BRD bit in IrCon for 1 152 Mbit sec FIR Fixed at 4 Mbit sec 17 3 2 2 Transmitting Data 17 3 2 2 1 Initialization The principal method of data transfer from memory to the active IrDA encoder MIR or FIR is by DMA Typically DMA can be used to transfer data of any length into the transmit FIFO when requested by the infrared peripheral...

Page 600: ...e IrRIB register to clear the RFC bit 8 Select Transmit Underrun Action When DMA is used the TUS bit should be cleared 9 Enable Transmit Set the IrCtrl TXE Transmit Enable bit Also set IrCtrl RXE if receive is to be enabled If DMA is used also set IrDMACR TXDMAE and IrDMACR RXDMAE if receive is to be enabled 10 Preloading the Transmit FIFO Copy the first two full words of data into the transmit FI...

Page 601: ...x018 and if there are three trailing bytes write to 0x01C See Table 17 2 17 3 2 2 4 End of Frame Interrupt Once all the data sent to the FIFO has been taken by the Ir interface the FIFO will underrun When this occurs any data that has been preloaded into the IrDataTail register will be used and the Transmitted Frame Complete TFC interrupt will be generated 17 3 2 2 5 Disable Transmit Circuitry To ...

Page 602: ...f Frame Using Programmed I O If interrupt driven programmed I O is used instead of DMA every time the Receive Buffer Service RFS interrupt is serviced the IrFlag register must be read before the IrData register if the IrFlag values are needed Their Flag register gives information about error conditions that correspond to the data value at the head of the receive FIFO Note The IrRIB registers store...

Page 603: ...l not occur until the rest of the frame has been discarded At the end of a frame a valid end of frame EOF or an abort RAB a DMA request corresponding to the last word which may hold 1 2 3 or 4 bytes of valid data of the received frame will be raised DMA will take the word At that point the receive FIFO should be empty and the DMA request may be deasserted The DMA request will be reasserted when da...

Page 604: ...trol information buffer register or by writing a 1 to its status bit position 17 4 Medium IrDA Specific Features The MIR comprises a dedicated serial port and RZI modulator demodulator supporting the Infrared Data Association IrDA standard for transmission reception at 0 576 and 1 152 Mb s Frames contain an 8 bit address an optional control field a data field of any size that is a multiple of 8 bi...

Page 605: ...ssion by automatically inserting a zero after five consecutive ones are detected in the transmitted bit stream This technique is commonly referred to as bit stuffing and is transparent to the user The information field within a MIR frame is placed between the start and stop flags consisting of an 8 bit address an optional 8 bit control field a data field containing any multiple of 8 bits and a 16 ...

Page 606: ...tion requirements and transmission characteristics of the target system Usually a length is selected which maximizes the amount of data that can be transmitted per frame while allowing the CRC checker to be able to consistently detect all errors during transmission All data fields must be a multiple of 8 bits If a data field that is not a multiple of 8 bits is received an abort is signalled and th...

Page 607: ...counter incremented at the sample clock rate is used to generate a receive clock at the nominal data rate sample clock divided by 41 and two thirds The sample rate counter is reset on the detection of each positive going data transition indicating the RZI encoding of a 0 to ensure that synchronization with the incoming data stream is maintained 17 4 2 2 Receive Operation Once the MIR receiver is e...

Page 608: ...he receive buffer the receive logic compares it to the CRC CCITT value which is continuously calculated using the incoming data stream If they do not match the last byte that was placed within the receive buffer is also flagged with a CRC error The CRC value is not placed in the receive buffer The MIR protocol permits back to back frames to be received When this occurs three flags separate back to...

Page 609: ... frame or an unexpected termination of a frame in progress When normal frame completion is selected and an underrun occurs the transmit logic transmits the 16 bit CRC value calculated during the transmission of all data within the frame including the address and control bytes followed by a flag to denote the end of the frame The transmitter then transmits an SIP followed by a continuous transmissi...

Page 610: ... of four symbols DDs comprising a single 125 ms pulse within a 500 ms symbol period The 125 ms quarters of a symbol are known as chips The resulting signal waveform for the four data DDs is shown in Figure 17 2 and Figure 17 3 and shows modulation of the byte 10110001b which is constructed using four DBPs Note 1 Bits within each DBP are not reordered but the least significant DBP is transmitted fi...

Page 611: ...odifications the start stop flags and CRC are twice as long and instead of one start flag a preamble and start flag of differing length are used Figure 17 4 IrDA 4 0 Mbps Transmission Format 64 symbols 8 symbols 4 DDs 8 bits 4 DDs 8 bits 8180 DDs max 2045 bytes 16 DDs 32 bits 8 symbols Preamble Start Flag Address Control optional Data CRC 32 Stop Flag Start Flag 0000 1100 0000 1100 0110 0000 0110 ...

Page 612: ...ut instead treats all bytes between the address and the CRC as data Note that the control field is transmitted and received starting with its LSB and ending with its MSB 17 5 1 2 3 Data Field The data field can be any length which is a multiple of 8 bits from 0 to 2045 bytes The user determines the data field length according to the application requirements and transmission characteristics of the ...

Page 613: ... may be cleared by writing a one to its location Set the TAB and TFC bits in the FISR register then read the FISR register to clear all interrupts 3 Next the desired mode of operation is programmed in the control register Set the TXE and RXE bits in the IrCtrl register 4 Write 1 to 3 bytes to the appropriate IrDataTail register 5 Once the FIR is enabled transmission reception of data can begin on ...

Page 614: ... from being placed within the receive buffer When the temporary buffer is filled data values are pushed out one by one to the receive buffer The first data byte of a frame is the address If receiver address matching is enabled the received address is compared to the address programmed in the address match value field in one of the control registers If the two values are equal or if the incoming ad...

Page 615: ...mit Operation Immediately after enabling the FIR for transmission the user may either prime the transmit buffer by filling it with data see section Section 17 5 2 on page 17 17 for details or allow service requests to cause the CPU or DMA to fill the buffer once the FIR is enabled Once enabled the transmit logic issues a service request if its buffer is empty For each frame output a minimum of six...

Page 616: ...he FIR s transmitter is disabled Note that it is the responsibility of the user to ensure that a frame completes once every 500 ms such that a SIP pulse is produced keeping all low speed devices from interrupting transmission Because most IrDA compatible devices produce a SIP after each frame transmitted the user may only need to ensure that a frame is either transmitted or received by the FIR eve...

Page 617: ...infrared peripheral Since MIRCLK is 18 432 MHz PCLK can be as low as 3 68 MHz and as high as 66 MHz Any PCLK frequency in this range is allowable Any PCLK frequencies outside the range are not supported and will result in incorrect behavior of the MIR mode of the infrared peripheral therefore The tolerance of UARTCLK is defined by the UART to which it is connected UARTCLK frequency must accommodat...

Page 618: ...s byte wide access to the IrDA without using the APB The DMA block will pack unpack individual bytes so that it reads or writes full 32 bit words rather than individual bytes Accessing the IrDA via the APB this requires APB AHB bus bandwidth Then both a read and write are required for each 32 bit data word Assuming most bytes in a packet are moved either via the DMA interface or via 32 bit word ac...

Page 619: ...st done status Read only bit indicating that the FIR transmit module has completed transition of the current frame and that it is safe to disable the module using the EN control bits MD Medium done status Read only bit indicating that the MIR transmit module has completed transmission of the current frame and that it is safe to disable the module using the EN control bits LBM Loopback Mode for MIR...

Page 620: ... TXE IrCtrl Address 0x808B_0004 Default 0x0000_0000 Definition IrDA Control Register This register selects various operating parameters Note that the RXE and TXE bit must be cleared before selecting a different interface with the IrEnable register EN bits The other bits in this register may be changed while the interface is active Bit Descriptions RSVD Reserved Unknown During Read AME Address Matc...

Page 621: ...e is 0 576 Mbit s 1 MIR data rate is 1 152 Mbit s 0 Must be written to 0 IrAdrMatchVal Address 0x808B_0008 Read Write Default 0x0000_0000 Definition IrDA Address Match Value Register contains the 8 bit address match value field which is used by the receiver to selectively store only the data within the receive frames which have the same address For incoming frames which have the same address value...

Page 622: ... Descriptions RSVD Reserved Unknown During Read TBY Transmitter Busy Flag 0 Transmitter is idle or disabled or an abort is being transmitted 1 Transmit logic is currently transmitting a frame RIF Receiver In Frame 0 Receiver is in preamble start flag or is in hunt mode 1 Receiver is in a frame RSY Receiver Synchronized Flag 0 Receiver is in hunt mode 1 Receiver logic is synchronized within the inc...

Page 623: ...ted to place data into receive buffer while it was full The next data value in the buffer is the last piece of good data before the buffer was overrun CRE CRC Error 0 No CRC check errors encountered in the data 1 CRC calculated on the incoming data does not match CRC value contained within the received frame RAB Receiver Abort 0 No abort has been detected for the incoming frame 1 Abort detected du...

Page 624: ...ne of three addresses Bits two and three of the address determine how many bytes within the word are significant that is are intended for transmission If none of the address is written the register remains marked as empty and payload data will be read by the transmit logic from the 32 bit FIFO only The status of this register does not affect the TFS flag nor does it cause interrupts or DMA request...

Page 625: ...only the lower eleven bits are presented BFRE Buffered Framing Error 0 No framing errors were encountered during the last frame 1 A framing error occurred during the last frame causing the remainder of the frame to be discarded BROR Buffered Receive buffer Overrun 0 The receive buffer did not overrun during the last frame 1 Receive logic attempted to place data into receive buffer while it was ful...

Page 626: ...cates the received byte count Bit Descriptions RSVD Reserved Unknown During Read BC Byte Count The total number of valid bytes read by the receiver IrDMACR Address 0x808B_0028 Read Write Default 0x0000_0000 Definition IrDA DMA Control Register Bit Descriptions RSVD Reserved Unknown During Read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD BC 31 30 ...

Page 627: ...o 1 enables the private DMA interface to the receive FIFO SIRTR0 Address 0x808B_0030 Read Write Default 0x0000_0000 except that bit 4 is unknown at reset Definition IrDA Slow InfraRed Test Register 0 Bit Descriptions RSVD Reserved Unknown During Read SIREN The state of the SIREN after synchronization Read only SIROUT The state of SIROUT output from the InfraRed block Read only TXD The state of the...

Page 628: ...1 when the last data for a frame is read from the receive FIFO and the RFC bit is still set from a previous end of frame This bit is cleared by writing a 1 to this bit This is triggered if the RFC bit is already set before the last data from a frame is read from the IrData register It indicates that the data from the IrRIB register was lost This can occur if the CPU does not respond to the RFC int...

Page 629: ...er it is terminated with a CRC followed by a stop flag or terminated with an abort Writing a 1 to this bit clears it TFS Transmit buffer Service Request read only 0 Transmit buffer is full or transmitter disabled 1 Transmit buffer is not full and the transmitter is enabled DMA service is signaled The bit is automatically cleared after the buffer is filled MIMR Address 0x808B_0084 Read Write Defaul...

Page 630: ...efault 0x0000_0000 Definition MIR Interrupt Register The IrDA interrupt is asserted if any bit in the MIIR is high Bit Descriptions RSVD Reserved Unknown During Read RFL Logical AND of MIR RFL status bit and RFL mask bit RIL Logical AND of MIR RIL status bit and RIL mask bit RFC Logical AND of MIR RFC status bit and RFC mask bit RFS Logical AND of MIR RFS status bit and RFS mask bit TAB Logical AN...

Page 631: ...eceive Information Buffer Lost Set to a 1 when the last data for a frame is read from the receive FIFO via the IrData register and the RFC bit is still set from a previous end of frame It indicates that data in the IrRIB register for the previous frame was lost This can occur if the CPU does not respond to the RFC interrupt before another frame completes and is read from the IrData register by the...

Page 632: ... transmitted frame completes whether it is terminated with a CRC followed by a stop flag or terminated with an abort This bit is cleared by writing a 1 to this bit TFS Transmit buffer Service Request read only 0 Transmit buffer is full or transmitter disabled 1 Transmit buffer is not full and the transmitter is enabled DMA service is signaled The bit is automatically cleared after the buffer is fi...

Page 633: ... 0x0000_0000 Definition FIR Interrupt Register An interrupt is signalled from this block if any bit is high in the FIIR Bit Descriptions RSVD Reserved Unknown During Read RFL Logical AND of FIR RFL status bit and RFL mask bit RIL Logical AND of FIR RIL status bit and RIL mask bit RFC Logical AND of FIR RFC status bit and RFC mask bit RFS Logical AND of FIR RFS status bit and RFS mask bit TAB Logic...

Page 635: ...associated 16 bit read write data register and a control register Each counter is loaded with the value written to the data register immediately This value will then be decremented on the next active clock edge to arrive after the write When the timer counter decrements to 0 it will assert the appropriate interrupt The timer counters can be read at any time The clock source and mode is selectable ...

Page 636: ...use an interrupt The timer is controlled by a single enable bit When the timer is enabled it begins counting from zero and when it is disabled it is cleared back to zero When it reaches its maximum value 0xFF_FFFF_FFFF it wraps around to zero and continues counting upwards 18 2 Registers Table 18 1 Timers Register Map Address Read Location Write Location Size Reset Value 0x8081_0000 Timer1Load Tim...

Page 637: ...bled The Timer Value register is updated with the Timer Load value as soon as the Timer Load register is written The Load register should not be written after the Timer is enabled because this causes the Timer Value register to be updated with an undetermined value Bit Descriptions RSVD Reserved Unknown During Read Load Initial load value of the timer Timer3Load Address Timer3 0x8081_0080 Read Wri...

Page 638: ...Timer Value register to be updated with an undetermined value Bit Descriptions Load Initial load value of the timer Timer1Value Timer2Value Address Timer1 0x8081_0004 Read Only Timer2 0x8081_0024 Read Only Reset Value 0x0000_0000 Definition The Value location gives the current value of the timer When the Timer Load register is written to the Value register is also updated with this Load value Bit ...

Page 639: ... Load value Bit Descriptions Value Current value of the timer Timer1Clear Timer2Clear Timer3Clear Address Timer1 0x8081_000C Write Only Timer2 0x8081_002C Write Only Timer3 0x8081_008C Write Only Reset Value Not defined Definition Writing any value to the Clear location clears an interrupt generated by the timer Bit Descriptions RSVD This register has no readable bits It is just a write trigger 31...

Page 640: ...operation ENABLE Timer enable bit This bit must be set to 1 to enable the timer When the timer is disabled its clock sources are turned off Before re enabling the timer its Load register must be written to again MODE This bit sets the mode of operation of the timer When set to 1 the timer is in periodic timer mode and when set to 0 the timer is in free running mode CLKSEL When set to 1 the 508 kHz...

Page 641: ...0000_0000 Definition This is a 9 bit read write register Enable is the only bit that matters during a register write When set to 1 the timer is enabled and begins to count upwards When set to 0 the debug timer registers are cleared to all zeros and the timer stops counting Timer4ValueHigh is a read only value and contains the high byte of the Timer4 counter Note that the Timer4ValueLow register mu...

Page 642: ...M1 Copyright 2007 Cirrus Logic Timers EP93xx User s Guide 1818 18 Bit Descriptions RSVD Reserved Unknown during a Read operation Enable Read Write Enable for Timer4 Value Read only High Byte of the Timer4 counter ...

Page 643: ... must reset the Watchdog timer sometimes known as kick the dog to a predetermined count on a periodic basis This resets the counter which prevents the WATCH_RESETn from activating The counter is reset by writing 0x5555 to the Watchdog register The Watchdog should be reset at least 2 WATCHDOG_CLK periods earlier than the time out calculation would indicate due to clock synchronization and handshaki...

Page 644: ... PWR_RESETn This is the power on reset input for resetting everything including reset status bits The power on reset is generated by a combination of the external PRSTn pin and the on chip voltage monitor power up detector RESET_KEYS_DETECTED The Watchdog will time out if the three key reset signal from the key scanning controller is activated This input disables the ability to reset the Watchdog ...

Page 645: ...er Bit Descriptions RSVD Reserved Unknown during read WRITE ONLY BIT FIELDS CTL Watchdog control bits The ARM Core writes 0x5555 to this half word to periodically restart the watchdog timer Writing 0xAA55 to this hword will disable the watchdog timer Writing 0xAAAA to this hword will re enable the watchdog timer Table 19 1 Watchdog Timer Register Memory Map Address Name SW locked Type Size Descrip...

Page 646: ...the watchdog software disable function This bit is active high when the watchdog is software disabled HWDIS Hardware Watchdog Disable The HWDIS bit monitors the HW_WATCHDOG_DISABLEN latch status in the watchdog module This provides status of the watchdog hardware disable function This bit is active high when the watchdog is hardware disabled URST User Reset Status flip flop Read only When 1 this b...

Page 647: ... be cleared by power on reset Bit Descriptions RSVD Reserved Unknown during read STAT Watchdog Status bits This is a watchdog status storage register that is not cleared by any resets other than power on reset and PWR_RESETn The system can be reset by a three key reset a user reset or a watchdog reset without losing the contents of this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD...

Page 649: ...Note The 32 768 Hz clock is referred to as the 32 kHz clock throughout the text 20 1 1 Software Trim The Real Time Clock oscillator software compensation circuitry allows software controlled digital compensation of a 32 768 kHz crystal oscillator Typically crystal oscillators must be externally compensated using discrete components They are mechanically calibrated during manufacture Software contr...

Page 650: ... compensation via deleting clocks at a fixed interval By measuring the frequency of the reference crystal and setting the RTCSWComp register value the clock can be adjusted to a nominal accuracy of better than 5 seconds per month 20 1 1 2 Oscillator Frequency Calibration Manufacturing can use a high precision frequency counter to measure the RTC 32 768 kHz reference clock via the EGPIO 1 pin when ...

Page 651: ... value Since the compensation procedure is performed only every 32 seconds the value must be set to delete 0 870 32 27 84 which when rounded is 28 clocks every 32 seconds The rounded 0 16 cycles per 32 seconds or 0 005 Hz represents the error in compensation The RTCSWComp DEL 4 0 fractional compensation value should be loaded with the hexadecimal equivalent of 28 1 or 0x1B 20 1 1 5 Maximum Error C...

Page 652: ... by PRSTn RTCData RTCMatch RTCLoad and RTCCtrl 20 1 Registers Register Descriptions RTCData Address 0x8092_0000 Read Only Default 0x0000_0000 Definition RTC Data Register Contains the 32 bit RTC counter value This counter is incremented by the 1 Hz clock output from the RTC Trim module Bit Descriptions RTCDR Counter value Table 20 1 Real Time Clock Register Memory Map Address Name Description 0x80...

Page 653: ...s set to 1 Bit Descriptions RTCMR Match value RTCSts Address 0x8092_0008 Read Write Default 0x0000_0000 Definition RTC Interrupt Status and End Of Interrupt Register Writing to this register clears the asserted interrupt Bit Descriptions RSVD Reserved unknown during read INTR Interrupt status 1 RTC interrupt is asserted 0 no interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCMR 15 14 13 ...

Page 654: ... Bit Descriptions RTCLR Load value RTCCtrl Address 0x8092_0010 Read Write Default 0x0000_0000 Definition RTC Interrupt Control Register Contains the interrupt enable control bit Bit Descriptions RSVD Reserved unknown during read MIE Match Interrupt Enable 1 RTC match interrupt is enabled 0 interrupt disabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCLR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 655: ...umber of 32 768 KHZ clocks to delete every 32 seconds for compensating the oscillator The value defaults to 0x0 which deletes no clock pulses INT Counter pre load Integer value This value is pre loaded into the counter as the integer divide portion of the oscillator compensation If set to 0x0000 no integer divide occurs and no clock pulses are deleted The value defaults to 0x7FFF which causes the ...

Page 657: ...ugh the ARM APB or DMA accesses Figure 21 1 gives an architectural overview of the I2S controller Table 21 1 lists the I2S controller input and output signals The i2s_audioclk_mux section performs gating on the incoming audio clocks based on the settings within the TX and RX clock configuration registers and delivers a known clock definition to the rest of the I2 S controller Figure 21 1 Architect...

Page 658: ... to the audio bit clock and word clock SCLK and LRCK that are generated see Chapter 5 Clock Control on page 5 4 for additional details The key features of the I2S transmitter are Three transmit data channels master or slave mode Table 21 1 I2 S Controller Input and Output Signals Signal Name Type Description lrck IN Left right Word Audio slave clock sck IN Audio bit slave clock sdi0 IN Serial data...

Page 659: ...2SGlCtrl 0 must be written to in order to turn on the PCLK to the I2 S controller The I2 S controller will not function correctly if this is not done 2 Write to the FIFO Once the I2 S controller is enabled the TX FIFO may be written to by either the DMA or the ARM Each FIFO is split up into 8 locations Each location consists of 2 X 32bit register and can hold one left and one right stereo sample 1...

Page 660: ...rallel loaded into the shift register and is serially shifted out the I2S sdo0 line If the I2 S controller is programmed to transmit 16 or 24 bit words the lower 16 or 24 bits are taken from the holding registers and loaded into the shift register The upper bits are ignored by the I2 S controller When the right sample is loaded into the shift register the I2S controller reads the next left and rig...

Page 661: ...page 448 To clear the underflow the programmer must write at least one left and right stereo sample to the FIFO Disabling the I2S controller will also clear the underflow The status of each FIFO is reflected in the Global Control Status register There are 5 bits for each FIFO in this register that reflect the state of the FIFO They are as follows Tx0_underflow Gets set when the I2 S controller rea...

Page 662: ...wait until the start of the next incoming left stereo word as indicated by the audio word clock When the start of the left word occurs the I2S controller will sample the data line and load each bit into a dedicated left shift register At the end of the left word and start of the right word as indicated by the audio word clock the contents of the left shift register are loaded into a left data regi...

Page 663: ...locations the FIFO overflow flag in the Global Control Status Register is asserted and an interrupt is asserted if enabled The Status Register bit and interrupt is cleared by reading a left right stereo sample pair from this FIFO location The data in the FIFO s is always right justified for word lengths of 16 and 24 bits The upper bits will be set to zero by the I2S controller in this case The I2 ...

Page 664: ...iguration register in order to ensure correct operation of the receiver The word lengths for both the TX and RX must be the same If the Transmitter is disabled and the Receiver is required to be in master mode then the i2s_mstr_clk_cfg output is generated from the I2SRXClkCfg register and the RX word length register Please note the I2SClkDiv Addr 0x8093_008C register in the SYSCON block has an eff...

Page 665: ... to SCLK Edge When SPOL 1 and i2s_mstr_clk_cfg 3 0 transition of output data bit and LRCK align to falling edge of SCLK When SPOL 0 and i2s_mstr_clk_cfg 3 1 transition of output data bit and LRCK align to rising edge of SCLK The output data bit is always a half cycle later to the SCLK edge which aligns to LRCK transition If the SCLK rising edge is configured to align to the LRCK transition then ou...

Page 666: ...e Format for Right Justified Data 21 6 Interrupts The I2S controller generates a single interrupt I2SINTR to the ARM Core This interrupt is a combination logical OR of all TX and RX internal interrupts The transmitter generates 4 internal interrupts within the I2S controller Each of these reflect the status of the 3 individual TX FIFOs These internal interrupts are as follows TX0 FIFO empty TX1 FI...

Page 667: ...nterrupts are as follows RX0 FIFO full RX1 FIFO full RX2 FIFO full RX overflow The first three can have their interrupt level determined by I2SRXCtrl 0 If this bit 1 then the FIFO full interrupt will occur when the FIFO is full If this bit 0 then the FIFO full interrupt will occur when the FIFO is half full All four are combined and are maskable with the RX interrupt register enable bit I2SRXCtrl ...

Page 668: ... and status bit Sticky bit Table 21 7 I2 S TX Registers Address Type Width Reset Value Name Description 0x8082_0010 R W 32 0x0 I2STX0Lft Left Transmit data register for channel 0 0x8082_0014 R W 32 0x0 I2STX0Rt Right Transmit data register for channel 0 0x8082_0018 R W 32 0x0 I2STX1Lft Left Transmit data register for channel 1 0x8082_001C R W 32 0x0 I2STX1Rt Right Transmit data register for channe...

Page 669: ...x0_left Transmit left data word for channel 0 I2STX0Rt Address 0x8082_0014 Read Write Default 0x0000_0000 Definition Transmit right data word for channel 0 Bit Descriptions i2s_tx0_right Transmit right data word for channel 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2s_tx0_left 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i2s_tx0_left 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2s_tx0_right ...

Page 670: ... left data word for channel 1 I2STX1Rt Address 0x8082_001C Read Write Default 0x0000_0000 Definition Transmit right data word for channel 1 Bit Descriptions i2s_tx1_right Transmit right data word for channel 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2s_tx1_left 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i2s_tx1_left 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2s_tx1_right 15 14 13 12 11 1...

Page 671: ...t left data word for channel 2 I2STX2Rt Address 0x8082_0024 Read Write Default 0x0000_0000 Definition Transmit right data word for channel 2 Bit Descriptions i2s_tx2_right Transmit right data word for channel 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2s_tx2_left 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i2s_tx2_left 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2s_tx2_right 15 14 13 12 11 ...

Page 672: ...d 1 right justified TXUF_REPEAT_SAMPLE On TX underflow the I2 S controller transmits all zeros if this bit is 1 If this bit is 0 the I2 S controller repeats the last sample on underflow TXDIR Transmit data shift direction 0 MSB first 1 LSB first I2STXCtrl Address 0x8082_002C Read Write Default 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RS...

Page 673: ...half empty 1 Generate interrupt when FIFO is empty I2STXWrdLen Address 0x8082_0030 Read Write Default 0x0000_0000 Definition Transmit Word Length Bit Descriptions RSVD Reserved Unknown During Read WL Transmit Word Length 00 16 bit mode 01 24 bit mode 10 32 bit mode I2STX0En Address 0x8082_0034 Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSV...

Page 674: ...ess 0x8082_0038 Read Write Default 0x0000_0000 Definition TX1 Channel Enable Bit Descriptions RSVD Reserved Unknown During Read i2s_tx1_EN TX1 Channel Enable I2STX2En Address 0x8082_003C Read Write Default 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD i2s_tx1_EN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 ...

Page 675: ... Reset Value Name Description 0x8082_0040 R 32 0x0 I2SRX0Lft Left Receive data register for channel 0 0x8082_0044 R 32 0x0 I2SRX0Rt Right Receive data register for channel 0 0x8082_0048 R 32 0x0 I2SRX1Lft Left Receive data register for channel 1 0x8082_004C R 32 0x0 I2SRX1Rt Right Receive data register for channel 1 0x8082_0050 R 32 0x0 I2SRX2Lft Left Receive data register for channel 2 0x8082_005...

Page 676: ...ht data word for channel 0 Bit Descriptions i2s_rx0_right Receive right data word for channel 0 I2SRX1Lft Address 0x8082_0048 Read Only Default 0x0000_0000 Definition Receive left data word for channel 1 Bit Descriptions i2s_rx1_left Receive left data word for channel 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2s_rx0_right 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i2s_rx0_right 31 30 29 28 27 ...

Page 677: ...ve right data word for channel 1 I2SRX2Lft Address 0x8082_0050 Read Only Default 0x0000_0000 Definition Receive left data word for channel 2 Bit Descriptions i2s_rx2_left Receive left data word for channel 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2s_rx1_right 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i2s_rx1_right 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2s_rx2_left 15 14 13 12 11 10...

Page 678: ...e Default 0x0000_0000 Definition Receive Line Control Data Register Bit Descriptions RSVD Reserved Unknown During Read Must be written as 0 Left_Right_Justify Receiver Data word Justification when being received on the SDI line input 0 Left justification 1 Right justification 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i2s_rx2_right 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i2s_rx2_right 31 30 29 ...

Page 679: ...e written as 0 ROFLIE Receive interrupt enable Active high RXFull_int_level Rx full interrupt level select 0 Generate interrupt when FIFO is half full 1 Generate interrupt when FIFO is full I2SRXWrdLen Address 0x8082_0060 Read Write Default 0x0000_0000 Definition Word Length 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD ROFLIE RXFull_int_level 31 3...

Page 680: ...Write Default 0x0000_0000 Definition RX0 Channel Enable Bit Descriptions RSVD Reserved Unknown During Read Must be written as 0 i2s_rx0_EN RX0 Channel Enable I2SRX1En Address 0x8082_0068 Read Write Default 0x0000_0000 Definition RX1 Channel Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD i2s_rx0_EN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ...

Page 681: ...21 7 3 I2S Configuration and Status Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD i2s_rx2_EN Table 21 9 I2S Configuration and Status Registers Address Type Width Reset Value Name Description 0x8082_0000 R W 7 0x0 I2STXClkCfg Transmitter clock configuration register 0x8082_0004 R W 7 0x0 I2SRXClkCfg Receiver clock configuration register 0x...

Page 682: ...th is ignored 11 Bit clock rate is fixed at 128x Word length is ignored i2s_tx_nbcg Defines TX not bit clock gating mode If I2STXClkCfg 5 6 00 this bit defines the bit clock rate otherwise ignored Bit clock rate 32x if word length is 16 Bit clock rate 64x if word length is 32 Bit clock rate 64x if word length is 24 There is a special case when the word length is 24 If this bit 0 and the word lengt...

Page 683: ...f the bitclk and are considered valid during negative transitions 0 Negative clock polarity The lrckt and sdox lines change synchronously with the negative edge of the bitclk and are considered valid during positive transitions i2s_tlrs Defines the polarity of lrckt 0 if lrckt is low then it is the left word if lrckt is high then it is the right word 1 if lrckt is low then it is the right word if ...

Page 684: ...length is 24 the last 8 cycles are not gated off in each word i2s_mstr Defines if the RX Audio clocks are slave or master 0 slave mode 1 master mode i2s_rrel Determines the timing of the lrckr with respect to the sdix data inputs 0 Transition of lrckr occurs together with the first data bit 1 Transition of lrckr occurs one bitclk cycle before the first sdix data bit i2s_rckp Defines polarity of th...

Page 685: ... the overflow occurred Rx2_overflow when 1 RX2 FIFO has overflowed and the FIFO pointer is currently pointing at the last data received before the overflow occurred Tx0_overflow when 1 the tx0 FIFO is full and an attempt has been made to write data to it by the APB or DMA This bit is cleared by writing a 0 to it 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD rx2_fif o_half_ full rx2_fifo _em...

Page 686: ... is cleared by writing a 0 to it tx0_fifo_full when 1 FIFO is full otherwise not full tx0_fifo_empty when 1 FIFO is empty otherwise not empty tx0_fifo_half_empty when 1 FIFO is half empty otherwise less than half empty rx0_fifo_full when 1 FIFO is full otherwise not full rx0_fifo_empty when 1 FIFO is empty otherwise not empty rx0_fifo_half_full when 1 FIFO is half full otherwise less than half ful...

Page 687: ...LK is turned on for the I2 S All registers except for the data registers can be written without the I2S PCLK enabled The ARM provides its own clock cycles when writing to any of the control status registers When the I2S controller is required to transmit or receive data PCLK must be turned on via this register The I2 S controller loopback mode bit determines if TX channel 0 is connected to RX chan...

Page 689: ... modes The data for the FIFOs can be written via either the APB interface or the DMA channels 1 3 Table 22 1 lists the input and output signals for the AC 97 controller The AC 97 pins are multiplexed and may be used for the I2 S controller instead of AC 97 by setting DeviceCfg I2SonAC97 The AC 97 Controller can support up to four different sampling rates at a time To allow the controller to suppor...

Page 690: ...r must ensure that all slot data stored in the FIFO is at the same sampling rate The length of time before a timeout interrupt is generated Whether the FIFO is enabled or not The number of bits in the slot that is captured Whether the channel is enabled to receive data or not The transmit part of each channel is controlled via its AC97TXCR register This register controls the following Which slot t...

Page 691: ...us of the individual interrupt sources can be read from appropriate register The interrupts are ORed to create one interrupt AC97INTR for the AC 97 controller block 22 2 1 Channel Interrupts The individual interrupts that are generated by each transmit receive channel are described below The status of the interrupts can be read from the AC97RISRx or AC97ISRx registers and is masked in the AC97IEx ...

Page 692: ... AC97EOI register 22 2 2 2 WINT The Wake up interrupt is asserted when a wake up event will trigger the assertion of SDATAIN while the AC Link is powered down The wake up is caused by the external codec s GPIO pins which have been configured to generate a wake up event via the codec s GPIO pin Wake up Control register 0x52 An AC Link wake up interrupt is defined as a 0 to 1 transition on SDATAIN w...

Page 693: ...pback Testing A loopback test mode is available for system testing so that data transmitted on SDATAOUT can also be received on SDATAIN Loopback mode is entered when a 1 is written to the LOOP bit in AC97GCR register For normal operation the LOOP bit must always be 0 which is also the default state at reset Note For this test mode to work an external bit clock will need to be supplied 22 4 Registe...

Page 694: ...8_006C Read AC97SR4 Status register 0x8088_0070 Read AC97RISR4 Raw interrupt status register 0x8088_0074 Read AC97ISR4 Interrupt Status 0x8088_0078 Read Write AC97IE4 Interrupt Enable 0x8088_007C Reserved 0x8088_0080 Read Write AC97S1Data Data received transmitted on SLOT1 0x8088_0084 Read Write AC97S2Data Data received transmitted on SLOT2 0x8088_0088 Read Write AC97S12Data Data received transmit...

Page 695: ...to the transmit FIFO If the FIFOs are not enabled data is stored in the transmitter holding register the bottom word of the transmit FIFO For received words If the FIFOs are enabled the data received is pushed onto the receive FIFO If the FIFOs are not enabled the data received is stored in the receiving holding register the bottom word of the receive FIFO The receive FIFO is 21 bits wide The 21st...

Page 696: ...t when the receive FIFO is not empty and no further data is received for a period of time This time period is specified by the value written here The value is the number of frames that must occur without any data being received a count of the SYNC signal A write of 0 to this value disables the counter and no timeout interrupt is generated On reset the value is 0 The maximum count of 4096 will allo...

Page 697: ...SLOT10 data RX9 FIFO stores SLOT9 data RX8 FIFO stores SLOT8 data RX7 FIFO stores SLOT7 data RX6 FIFO stores SLOT6 data RX5 FIFO stores SLOT5 data RX4 FIFO stores SLOT4 data RX3 FIFO stores SLOT3 data RX2 FIFO stores SLOT2 data RX1 FIFO stores SLOT1 data REN A 1 written to this bit enables the receive for this FIFO and enables the PCLK for the respective channel Table 22 3 Interaction Between RSIZ...

Page 698: ...nd 2 data is to be sent via this FIFO it will always be transmitted at 48kHz Therefore it is advisable not to enable any other slots unless they too are sampled at 48kHz The data contained within the TSIZE bits controls the number of zeros that are to be appended to data to make it 20 bits Should two channels be enabled for the same data slot then data is taken from given to the lower channel numb...

Page 699: ...its to a data word See Table 22 4 for details of the interaction between RSIZE and CM 00 data is 16 bits 01 data is 18 bits 10 data is 20 bits 11 data is 12 bits TX12 FIFO stores SLOT12 data takes precedence over AC97S12Data TX11 FIFO stores SLOT11 data TX10 FIFO stores SLOT10 data TX9 FIFO stores SLOT9 data TX8 FIFO stores SLOT8 data TX7 FIFO stores SLOT7 data TX6 FIFO stores SLOT6 data TX5 FIFO ...

Page 700: ...eive status of the block After reset the TXFF RXFF and TXBUSY are 0 and TXFE and RXFE are 1 Bit Descriptions RSVD Reserved Unknown During Read TXUE TX Underrun Error This bit is set to 1 if an underrun error has been detected if data is to be transmitted and the FIFO is empty This bit is cleared to 0 by writing to the AC97DR register Note Bit will only be set if FIFO had been written to at least o...

Page 701: ...E Receive FIFO empty flag active HIGH This bit is asserted HIGH if the receive FIFO is empty AC97RISRx Address AC97RISR1 0x8088_0010 Read Only AC97RISR2 0x8088_0030 Read Only AC97RISR3 0x8088_0050 Read Only AC97RISR4 0x8088_0070 Read Only Definition Raw Interrupt Status The AC97ISR registers are the raw Interrupt status registers for the controller FIFOs All bits are cleared to zero on reset excep...

Page 702: ...terrupt status registers for the controller FIFOs All bits are cleared to zero on reset except for the TCIS as the FIFO and shift register should both be empty Bit Descriptions RSVD Reserved Unknown During Read RIS RX Interrupt Status If this bit is set to 1 the receive FIFO interrupt is asserted TIS TX Interrupt Status If this bit is set to 1 the transmit FIFO interrupt is asserted RTIS RX Timeou...

Page 703: ...ansmit Interrupt Enable If this bit is set to 1 the FIFO transmit interrupt is enabled RTIE Receive Timeout Interrupt Enable If this bit is set to 1 the FIFO receive timeout interrupt is enabled TCIE Transmit Complete Interrupt Enable If this bit is set to 1 the FIFO transmit complete interrupt is enabled AC97S1Data Address 0x8088_0080 Read Write Definition Slot 1 Data Register The AC97S1Data regi...

Page 704: ...r AC97S2Data register If a power down is required then the software must write the address 0x26 to this location for the external device which will be recorded by the controller If the AC97S2Data bit 12 is set then the controller will go into power down mode Bit Descriptions RSVD Reserved Unknown During Read DATA Read operation Read data value of the last value written to this register via the AC ...

Page 705: ... next available frame Once the data has been transmitted it will marked as invalid AC97S12Data Address 0x8088_0088 Read Write Definition Slot 12 Data Register The AC97S12Data register is a read write register Data written to it will be sent on the next available frame in SLOT 12 When this register is read the data contained within it is the data that was last received for SLOT 12 Bit Descriptions ...

Page 706: ...s set to 1 The RAW Wake up interrupt is asserted This bit is cleared with a write to the AC97EOI register GPIOINT The GPIOINT shows the raw status of the GPIOINT bit slot 12 bit 0 in the receive frame which is stored in the AC97S12Data register This bit is cleared when the AC97S12Data register is read GPIOTXCOMPLETE GPIO Transmission Complete Set when a new value to the AC97S12Data register has co...

Page 707: ...READY This bit is set to 1 during a wakeup when the codec indicates that it is ready by setting bit 15 of Slot0 WINT Wake up Interrupt Status If this bit is set to 1 the Wake up Interrupt is asserted GPIOINT GPIO Interrupt Status If this bit is set to 1 the GPIOINT interrupt is asserted GPIOTXCOMPLETE If this bit is set to 1 the GPIOTXCOMPLETE interrupt is asserted SLOT2RXVALID If this bit is set ...

Page 708: ...ady Interrupt is enabled WINT If this bit is set to 1 the Wake up Interrupt is enabled GPIOINT If this bit is set to 1 the GPIO interrupt is enabled GPIOTXCOMPLETE If this bit is set to 1 the GPIOTXCOMPLETE interrupt is enabled SLOT2RXVALID If this bit is set to 1 SLOT2RXVALID interrupt is enabled SLOT1TXCOMPLETE If this bit is set to 1 SLOT1TXCOMPLETE interrupt is enabled AC97EOI Address 0x8088_0...

Page 709: ...ad Write Definition Global Control Register The AC97GCR register is the main control register for the AC 97 Controller All bits are cleared on reset The AC97IFE creates the clock enable signal for the clock controller block It is used to enable disable both PCLK and AC97LK Bit Descriptions RSVD Reserved Unknown During Read OCODECReady If set to 1 this bit will override normal CODEC ready definitio...

Page 710: ...no effect FORCEDRESET If the EFORCER bit is set to 1 the RESET port will follow whatever value is written to this bit If this mechanism is used to control the RESET port it is up to software to ensure that the signal is high long enough to meet the specification of the external device This bit has priority over the TIMEDRESET bit TIMEDRESET If this bit is set to 1 the RESET port is forced to 0 for...

Page 711: ...If EFORCES bit is set to 1 the SYNC port will follow whatever value is written to this bit If this mechanism is used to control the SYNC port it is up to software to ensure that the signal is high long enough to meet the specification of the external device This bit has priority over the TIMEDSYNC bit TIMEDSYNC If this bit is set to 1 the SYNC port is forced to 1 for five pulses of the 2 9491 MHz ...

Page 712: ...ers in the controller This register allows the software to read all the interrupt sources with one read Bit Descriptions RSVD Reserved Unknown During Read AC97GIS Copy of the AC97GIS register AC97ISR4 Copy of the AC97ISR 4 register AC97ISR3 Copy of the AC97ISR 3 register AC97ISR2 Copy of the AC97ISR 2 register AC97ISR1 Copy of the AC97ISR 1 register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 713: ...tted on SSPTXD and received on SSPRXD 23 2 Features Following is a list of features of the Synchronous Serial Port Master or Slave operation Programmable clock bit rate and prescaler Separate transmit and receive FIFO memory buffers 16 bits wide 8 locations deep Programmable data frame size from 4 to 16 bits Independent masking of transmit FIFO receive FIFO and receive overrun interrupts The SSP h...

Page 714: ...I2S controller instead of SSP by setting DeviceCfg I2SonSSP 23 5 Configuring the SSP Following reset the SSP logic is disabled and must be configured when in this state Control registers SSPCR0 and SSPCR1 need to be programmed to configure the peripheral as a master or slave operating under one of the following protocols Motorola SPI Texas Instruments SSI National Semiconductor The bit rate derive...

Page 715: ... the SSP is idle and transitions at the programmed frequency only during active transmission or reception of data The idle state of SCLKOUT is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period For Motorola SPI and National Semiconductor Microwire frame formats the serial frame SFRMOUT pin is active LOW and is asserted pull...

Page 716: ...l shift register of the transmit logic On the next rising edge of SCLKOUT the MSB of the 4 to 16 bit data frame is shifted out on the SSPTXD pin Likewise the MSB of the received data is shifted onto the SSPRXD pin by the off chip serial slave device Both the SSP and the off chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SCLKOUT The received ...

Page 717: ...he SCLKOUT pin when data is not being transferred 23 5 6 2 SPH Clock Phase The SPH control bit selects the clock edge that captures data and allows it to change state It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge When the SPH phase control bit is LOW data is captured on the first clock edge transition If...

Page 718: ... that both the master and slave data have been set the SCLKOUT master clock pin goes HIGH after one further half SCLKOUT period The data is now captured on the rising edges and is propagated on the falling edges of the SCLKOUT signal In the case of a single word transmission after all bits of the data word have been transferred the SFRMOUT line is returned to its idle HIGH state one SCLKOUT period...

Page 719: ...e If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SFRMOUT master signal being driven LOW The master SSPTXD output pad is enabled After a further one half SCLKOUT period both master and slave valid data is enabled onto their respective transmission lines At the same time the SCLKOUT is enabled with a rising edge transition Data is...

Page 720: ...PI Frame Format Continuous Transfer with SPO 1 and SPH 0 In this configuration during idle periods the SCLKOUT signal is forced HIGH SFRMOUT is forced HIGH the transmit data line SSPTXD is arbitrarily forced LOW when the SSP is configured as a master the SSPCTLOE line is driven LOW enabling the SCLKOUT pad active LOW enable when the SSP is configured as a slave the SSPCTLOE line is driven HIGH dis...

Page 721: ...ever in the case of continuous back to back transmissions the SFRMOUT signal must be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero Therefore the master device must raise the SFRMIN pin of the slave device between each data transfer to enable the ser...

Page 722: ...ng edges of the SCLKOUT signal After all bits have been transferred in the case of a single word transmission the SFRMOUT line is returned to its idle HIGH state one SCLKOUT period after the last bit has been captured For continuous back to back transmissions the SFRMOUT pins remains in its active LOW state until the final bit of the last word has been captured and then returns to its idle state a...

Page 723: ...or the duration of the frame transmission The SSPRXD pin remains in a high impedance state during this transmission The off chip serial slave device latches each control bit into its serial shifter on the rising edge of each SCLKOUT After the last bit is latched by the slave device the control byte is decoded during a one clock wait state and the slave responds by transmitting data back to the SSP...

Page 724: ...t to the rising edge of SCLKIN Figure 23 11 illustrates these setup and hold time requirements With respect to the SCLKIN rising edge on which the first bit of receive data is to be sampled by the SSP slave SFRMIN must have a setup of at least two times the period of SCLKIN on which the SSP operates With respect to the SCLKIN rising edge previous to this edge SFRMIN must have a hold of at least on...

Page 725: ... Description Address Type Width Reset value Name Description 0x808A_0000 Read write 16 0x0000 SSPCR0 Control register 0 0x808A_0004 Read write 8 0x00 SSPCR1 Control register 1 0x808A_0008 Read write 16 0x0000 SSPDR Receive FIFO Read Transmit FIFO data register Write 0x808A_000C Read 7 0x00 SSPSR Status register 0x808A_0010 Read write 8 0x00 SSPCPSR Clock prescale register 0x808A_0014 Read 3 0x0 SS...

Page 726: ...me format 00 Motorola SPI frame format 01 TI synchronous serial frame format 10 National Semiconductor Microwire frame format 11 Reserved undefined operation DSS Data Size Select 0000 Reserved undefined operation 0001 Reserved undefined operation 0010 Reserved undefined operation 0011 4 bit data 0100 5 bit data 0101 6 bit data 0110 7 bit data 0111 8 bit data 1000 9 bit data 1001 10 bit data 1010 1...

Page 727: ...SSPTXD line 0 SSP may drive the SSPTXD output in slave mode 1 SSP must not drive the SSPTXD output in slave modes MS Master Slave mode select This bit can be modified only when the SSP is disabled SSE 0 0 Device configured as master default 1 Device configured as slave SSE Synchronous serial port enable 0 SSP operation disabled 1 SSP operation enabled LBM Loop back mode 0 Normal serial port operat...

Page 728: ...ritten Data values are removed from the transmit FIFO one value at a time by the transmit logic It is loaded into the transmit serial shifter then serially shifted out onto the SSPTXD pin at the programmed bit rate When a data size of less than 16 bits is selected the user must right justify data written to the transmit FIFO The transmit logic ignores the unused bits Received data less than 16 bit...

Page 729: ...indicate the FIFO fill status and the SSP busy status Bit Descriptions RSVD Reserved Unknown During Read BSY SSP busy flag read only 0 SSP is idle 1 SSP is currently transmitting and or receiving a frame or the transmit FIFO is non empty RFF Receive FIFO full read only 0 Receive FIFO is not full 1 Receive FIFO is full RNE Receive FIFO not empty read only 0 Receive FIFO is empty 1 Receive FIFO is n...

Page 730: ...r data read back from this register will have the least significant bit as zero Bit Descriptions RSVD Reserved Unknown During Read CPSDVSR Clock pre scale divisor Should be an even number from 2 to 254 depending on the frequency of SSPCLK The least significant bit CPSDVSR 0 always returns zero on reads since it is hard coded to 0 SSPIIR SSPICR Address 0x808A_0014 Read Only Note A write to this reg...

Page 731: ...Read RORIS Read SSP Receive FIFO overrun interrupt status 0 SSPRORINTR is not asserted 1 SSPRORINTR is asserted This bit is cleared by writing any value to the SSPSR register TIS Read SSP transmit FIFO service request interrupt status 0 SSPTXINTR is not asserted indicating that the transmit FIFO is more than half full 1 SSPTXINTR is asserted indicating that the transmit FIFO is less than half full...

Page 733: ...le 24 2 Theory of Operation Each PWM is an Advanced Microcontroller Bus Architecture AMBA compliant system on a chip SOC peripheral Each is a configurable dual output dual clock input AMBA slave module and each connects to the Advanced Peripheral Bus APB The PWM Interfaces comply with the AMBA Specifications Rev 2 0 This design assumes little endian memory organization Both of the PWM peripherals ...

Page 734: ...n is explained below Both PWMs are reset to the halted condition The output of either PWM can be programmed for either normal or inverted operation Inversion affects the output pin when the PWM peripheral is halted and also when it is running Both outputs are reset to the normal non inverted configuration which places the output pins in a LOW condition at reset When the output is reprogrammed to b...

Page 735: ...th PWMxTermCnt and PWMxDutyCycle are updated 2 Program PWMxTermCnt and PWMxDutyCycle with values that meet the specification 3 When PWM is stopped PWM_EN 0 it does not stop immediately but waits for the end of the current PWM cycle and then stops 24 3 Registers Note All pwmout outputs will drive a logical 0 during reset Coming out of reset it will continue to drive a logical 0 and the PWM will be ...

Page 736: ... PWMxTermCnt gives the PWM up to 16 bit resolution PWMxTermCnt is double buffered to allow it to be programed statically PWM is stopped or dynamically PWM is running Programmed dynamically PWMxTermCnt is updated at the end of a PWM cycle to prevent any output glitches or errors Reading the register reflects what was written to it not the state of the counter PWMxDutyCycle Address PWM0DutyCycle 0x8...

Page 737: ...e state of the counter PWMxEn Address PWM0En 0x8091_0008 Read Write PWM1En 0x8091_0028 Read Write Default 0x0000_0000 Definition PWMx Enable Bit Descriptions RSVD Reserved Unknown During Read EN Enable PWM 0 Disable Stop PWM The PWM is actually stopped when it reaches the end of its current cycle PWM output is 0 If PWM_INV 0 1 if PWM_INV 1 1 PWM is Enabled When in normal mode writing a one will st...

Page 738: ...amically PWM is running Programmed statically the invert takes affect after the APB write completes and CLK_PWM is running After the update CLK_PWM can be turned off without affecting PWMOUT In this way the PWM output can be inverted without enabling the PWM Programmed dynamically PWM_INV is updated at the end of a PWM cycle to prevent any output glitches or errors Read write accesses to PWM_INV w...

Page 739: ...thms if desired However the hardware engine provides all features necessary to implement a standard interface and eliminates almost all ARM Core intervention in the scanning process For both X and Y axes the touch screen controller engine does the following Takes 4 8 16 or 32 sample sets Checks to see if the deviation in the sample set is too great Averages the samples Checks the average to see if...

Page 740: ...r both of the Y lines and by then measuring a voltage driven between the bus bars on the Y axis layer through either or both of the X lines By comparing these voltages to values determined during calibration the location of the touch can be determined 4 WIRE ANALOG RESISTIVE TOUCH SCREEN SCHEMATIC X Y X Y 8 WIRE ANALOG RESISTIVE TOUCH SCREEN SCHEMATIC X Y X Y SX SY SX SY 5 WIRE ANALOG RESISTIVE TO...

Page 741: ...y controlled analog switches These switches may be connected in a variety of ways which allows a high degree of flexibility in using the analog to digital converter To avoid contention each switch drive circuit has a much faster turn off than turn on to provide an overall break before make array function Logic safeguards are included to condition the control signals for power connection to the mat...

Page 742: ...ided on the signals This is controlled by the DLY field in the TSSetup register The analog touch screen interface circuitry is internally connected to a signed 12 bit analog to digital converter The 12 bit digital result is held stable until another sample is requested The controller reads the digital value by issuing a read pulse This read pulse signal from the controller is also used as a conver...

Page 743: ...m are determined by configuration registers The configuration registers are set up by software according to the touch screen type Table 25 2 details the configuration values required for 4 5 6 and 8 wire touch screens Figure 25 2 8 Wire Resistive Interface Switching Diagram DISCHARGE ALL LINES SAMPLE X AXIS SAMPLE Y AXIS X X Y Y SX SX SY SY SW12 SW14 SW13 SW20 A D CONVERTER IN REF REF VDD SW21 SW1...

Page 744: ...R IN REF REF VDD SW21 SW19 SW11 SW0 SW1 SW2 SW3 SW24 SW25 SW26 SW27 100K SW23 SW22 100K SW9 SW10 SW6 SW7 SW4 SW5 SW15 SW16 SW17 SW18 X X Y Y not used SW12 SW14 SW13 SW20 A D CONVERTER IN REF REF VDD SW21 SW19 SW11 SW0 SW1 SW2 SW3 SW24 SW25 SW26 SW27 100K SW23 SW22 100K SW9 SW10 SW6 SW7 SW4 SW5 SW15 SW16 SW17 SW18 X X Y Y SW12 SW14 SW13 SW20 A D CONVERTER IN REF REF VDD SW21 SW19 SW11 SW0 SW1 SW2 S...

Page 745: ...le is compared with a min and max register to determine the range of samples taken The min register is initialized to a value of 4095 and the max register is initialized to a value of 0 Any data points sampled will fall within this range and the min and max stored sample values will be adjusted based on the comparison In addition as the samples are taken a running accumulator adds each 12 bit samp...

Page 746: ... set at this point to cause the algorithm to skip over the comparison to XMIN on consecutive sample sets This flag will also cause a ARM Core interrupt after valid X and Y samples have been established The algorithm then starts again discharging and detecting a valid press If the difference between the new X value and the last stored X value is less than the XMAX value the algorithm stores the new...

Page 747: ...VTMR carry Y N ABS X XLAST GREATER THAN XMAX Y N X INT PENDING Y N SET X INT PENDING XLAST X SCAN Y AXIS DISCHARGE ALL FOR PRESET SETTLING TIME APPLY VOLTAGE TO Y AXIS DELAY FOR PRESET SETTLING TIME TAKE 4 8 16 OR 32 SAMPLES STORING MAX MIN AND AVERAGE N SET X INT PENDING XLAST X N ABS X XLAST LESS THAN XMIN Y Y ABS Y YLAST GREATER THAN YMAX Y N Y INT PENDING Y N SET Y INT PENDING YLAST Y SET INTE...

Page 748: ...d the algorithm continues by moving to the settle state and detecting a valid press The interrupt is cleared when the TSXYResult register is read or by clearing the TSSetup2 TINT bit As can be seen from Figure 25 3 4 wire touch screens are operated in much the same way a 8 wire touch screens except that the reference for the A D converter is internal instead of a feedback The register values TSDet...

Page 749: ...D SW21 SW19 SW11 SW0 SW1 SW2 SW3 SW24 SW25 SW26 SW27 100K SW23 SW22 100K SW9 SW10 SW6 SW7 SW4 SW5 SW15 SW16 SW17 SW18 SW12 SW14 SW13 SW20 A D CONVERTER IN REF REF VDD SW21 SW19 SW11 SW0 SW1 SW2 SW3 SW24 SW25 SW26 SW27 100K SW23 SW22 100K SW9 SW10 SW6 SW7 SW4 SW5 SW15 SW16 SW17 SW18 V V Z Z Not used Not used Wiper Not used V V Z Z Not used Not used Wiper Not used Not used Not used Wiper Not used SW...

Page 750: ...OUCH_PRESS signal in the figure is gated into the interrupt logic when the touch screen controller is disabled and in low power mode In this mode the clock to the module can be disabled and interrupts will still be generated The low power mode should be entered and exited with the touch screen interrupt disabled as the asynchronous operation of this logic could cause glitches on the interrupt line...

Page 751: ...r feedback or other miscellaneous analog inputs when the touch screen controller is disabled Figure 25 8 shows the switch configuration for reading these values Note that any extra reference lines that are not used for 4 wire or 5 wire touch screens can be read from the APB bus by temporarily disabling the touch screen controller Please note that the initial read should be viewed as a convert comm...

Page 752: ... we need to configure 2 items in Syscon Enable the Clock for the Touch Screen KTDIV register in Syscon Set the TIN bit in DeviceCfg in Syscon This sets the Touch Screen controller to an inactive state Figure 25 8 Other Switching Diagrams Test DAC Measure Other Misc Input Not Used SW12 SW14 SW13 SW20 A D CONVERTER IN REF REF VDD SW21 SW19 SW11 SW0 SW1 SW2 SW3 SW24 SW25 SW26 SW27 100K SW23 SW22 100K...

Page 753: ...on indicates that the switch is made or closed Therefore the TSDirect value for 4 or 8 wire X axis resistance measurement should be set to 0x0040_1601 the TSDirect value for 4 or 8 wire Y axis resistance measurement should be set to 0x0080_4604 and the TSDirect value for 5 wire resistance measurement should be set to 0x0080_4604 See Figure 25 9 Figure 25 9 Measure Resistance Switching Diagram 4 8 ...

Page 754: ...ew valid value Conversion data may also be processed using interrupts from this module If bit 11 in the TSSetup2 register the RINTEN bit is set an interrupt occurs whenever the SDR bit in the TSXYResult register is set Therefore an interrupt handler can read the TSXYResult register whenever a new valid sample appears in the register which both returns a new conversion value and clears the interrup...

Page 755: ...e Touch Screen controller max min register 0x8090_0008 TSXYResult No Read Only 32 bits Analog Resistive Touch Screen controller result register 0x8090_000C TSDischarge Write Read Write 28 bits Analog Resistive Touch Screen controller Switch Matrix control register 0x8090_0010 TSXSample Write Read Write 28 bits Analog Resistive Touch Screen controller Switch Matrix control register 0x8090_0014 TSYS...

Page 756: ...etween A D samples from 3 to 1024 μsec assuming a 1 MHz clock NSMP Defines the number of samples averaged per X or Y reading 00 4 samples 01 8 samples 10 16 samples 11 32 samples DEV Defines the amount of max to min range deviation in a sample set allowed before rejection 000 4 LSBs 001 8 LSBs 010 12 LSBs 011 16 LSBs 100 24 LSBs 101 32 LSBs 110 64 LSBs 111 128 LSBs ENABLE Enables the touch screen ...

Page 757: ...n can be from 16 to 4096 in increments of 16 decode locations in a 4096 x 4096 decode array YMIN 7 0 XMIN 7 0 Defines the amount of x y distance from a previous touch value to a new touch value for a touch detection to initiate another interrupt to the ARM Core The x y box definition can be up to 512 x 512 256 TSXYResult Address 0x8090_0008 Default 0x0000_0000 Definition Analog Touch screen X and ...

Page 758: ...t resolution The interrupt output is cleared when this register is read AD AD_X Direct analog to digital controller output when touch screen controller is disabled at 16 bit resolution TSDischarge TSXSample TSYSample TSDirect TSDetect Address TSDischarge 0x8090_000C TSXSample 0x8090_0010 TSYSample 0x8090_0014 TSDirect 0x8090_0018 TSDetect 0x8090_001C Default 0x0000_0000 Definition Analog switch co...

Page 759: ...nknown during read SWLCK Software lock bits WRITE The Unlock value for this feature is 0xAA Writing 0xAA to this register will unlock all locked registers until the next block access The ARM lock instruction prefix should be used for the two consecutive write cycles when writing to locked chip registers READ During a read operation SWLCK 0 has the following meaning 1 Unlocked for current bus acces...

Page 760: ...ed by bit 28 NSIGND Unsigned ADC output type The touch input information can be processed as signed or unsigned integers The default bit value is 0 for signed DISDEV Disable Deviation check for both X and Y ADC sampling Setting this bit high causes the deviation test to always pass and forces a sample set DTMEN Deviation Timer Enable Setting this bit high enables the timeout for the deviation chec...

Page 761: ...wn PINT Pen up Interrupt This is the Pen up interrupt When the PINTEN bit is set and a pen up condition is detected after a pen down this bit will be set high and cause the interrupt output to go high This bit may be written high for test purposes and written low to clear the interrupt NICOR No Interrupt Clear on Read This bit controls clearing of the touch interrupt 0 TINT clears when reading TSX...

Page 763: ...upt interval between 24 and 44 milliseconds A low power wakeup mode A three key reset If the system does not use a keyboard the Row 7 0 and Column 7 0 pins can be remapped to General Purpose Input Output GPIO pins For details see Chapter 5 DeviceCfg on page 5 25 and Chapter 28 Table 28 4 on page 28 8 A block diagram for the key array scanning circuitry is shown in Figure 26 1 Figure 26 1 Key Array...

Page 764: ...with the binary column address Key addresses range from 0x00 to 0x3F A diagram of the key array is shown in Figure 26 2 The circuitry scans the key array by driving each ROW line low one line at a time At the end of each ROW time period column data is read The key array column lines are registered and decoded by a multiplexer The column address selects the column multiplexer input Each of the colu...

Page 765: ...prets the electrical signals as An apparent key address of 0x00 at ROW0 COL0 An actual key address of 0x03 at ROW0 COL3 No press for address 0x18 at ROW3 COL0 ROW 0 KEY 00H KEY 01H KEY 02H KEY 03H KEY 04H KEY 05H KEY 06H KEY 07H ROW 1 KEY 08H KEY 09H KEY 0AH KEY 0BH KEY 0CH KEY 0DH KEY 0EH KEY 1FH ROW 2 KEY 10H KEY 11H KEY 12H KEY 13H KEY 14H KEY 15H KEY 16H KEY 17H ROW 3 KEY 18H KEY 19H KEY 1AH K...

Page 766: ... the key 0x00 appears to be pressed Figure 26 3 Apparent Key 00H ROW 0 KEY 00H KEY 01H KEY 02H KEY 03H KEY 04H KEY 05H KEY 06H KEY 07H ROW 1 KEY 08H KEY 09H KEY 0AH KEY 0BH KEY 0CH KEY 0DH KEY 0EH KEY 1FH ROW 2 KEY 10H KEY 11H KEY 12H KEY 13H KEY 14H KEY 15H KEY 16H KEY 17H ROW 3 KEY 18H KEY 19H KEY 1AH KEY 1BH KEY 1CH KEY 1DH KEY 1EH KEY 1FH ROW 4 KEY 20H KEY 21H KEY 22H KEY 23H KEY 24H KEY 25H K...

Page 767: ...ge the key array between column samples is reduced To reduce the time to charge the key array the back drive feature may be used When back drive is enabled the column lines and row lines are all driven high for a short period of time between ROW scanning time to charge the array capacitance 26 2 3 Interrupt Generation An interrupt is generated whenever the key scanner detects a new stable set of k...

Page 768: ...y scanning circuitry provides a three key reset output by detecting keys columns 2 4 and 7 activated in row 0 The three key reset detect is used by the watchdog circuit to generate a three key initiated reset to the system The output RESET_KEYS_DETECTED goes to the Watchdog block to indicate that a three key reset is being requested 26 3 Registers Note Key scan controller registers are intended to...

Page 769: ...t to the watchdog reset block Setting it back low re enables it DIAG Key scan diagnostic mode Setting this bit high allows key scanning to be directly controlled through the key register by writes from the ARM Core The DIAG KEY 5 0 value is written by the ARM Core Then the KeyRegister K bit is read to determine if there is a key press The result from reading the KeyRegister K bit is not hardware d...

Page 770: ...rly for these values Key array scan time clock period PRSCL 1 64keys Example scan time for PRSCL 9 0 0x0FA Scan time 1 μs 249 1 16 ms if de bounce 0xFC key detection interrupt is fired in approximately 48 ms Array scan time can range from 64 μsec to 65 536 ms KeyDiagnostic Address 0x808F_0004 Default 0x0000_0000 Definition Diagnostic key value register Bit Descriptions RSVD Reserved Unknown during...

Page 771: ...terrupt line INTRQ from the device for interrupt service It also has an internally generated interrupt signal INTide for reporting internal errors in the IDE host to the ARM Core The IDE port is connected to the external ATAPI device through a 28 pin interface Of these 28 signals 25 use dedicated pins 2 share EGPIO pins EGPIO 2 for DMARQ and EGPIO 15 for DASPn and the device interrupt request uses...

Page 772: ...1 Strobe signal to read device regs or data port Flow control signal for Ultra DMA data in burst Flow control signal for Ultra DMA data out burst DIOWn STOP 1 Strobe signal to write device regs or data port Terminates an Ultra DMA burst DMACKn 1 DMA acknowledge to DMARQ to initiate DMA transfers DASPn GPIO 1 Signal to indicate that a device is active or that Device 1 is present DMARQ GPIO 1 DMA re...

Page 773: ...PIO mode PIO Mode 0 Delay for 70 ns PIO Mode 1 Delay for 50 ns PIO Mode 2 Delay for 30 ns PIO Mode 3 Delay for 30 ns PIO Mode 4 Delay for 25 ns 3 Bring DIORn high 4 Based on the PIO mode delay as follows before the next read or write can occur PIO Mode 0 Delay for 290 ns PIO Mode 1 Delay for 290 ns PIO Mode 2 Delay for 290 ns PIO Mode 3 Delay for 80 ns PIO Mode 4 Delay for 70 ns 5 Bring DIORn low ...

Page 774: ...xt read or write can occur PIO Mode 0 240 ns PIO Mode 1 50 ns PIO Mode 2 20 ns PIO Mode 3 70 ns PIO Mode 4 25 ns Minimum total cycle time for the various PIO modes is as follows PIO Mode 0 600 ns PIO Mode 1 383 ns PIO Mode 2 330 ns PIO Mode 3 180 ns PIO Mode 4 120 ns You must also setup IDECFG and WST as follows according to the PIO mode PIO Mode 0 Delay for 30 ns PIO Mode 1 Delay for 20 ns PIO Mo...

Page 775: ...ntrolling when to toggle HSTROBE and by the device through temporarily deasserting DDMARDYn In a read operation the state machine does the handshaking and starts to receive data from the device When the read buffer has 4 or more entries filled a DMA request is sent to the DMA controller Flow control is achieved by the host through temporarily deasserting HDMARDYn or by the device through controlli...

Page 776: ... exists when the DMA request conflicts with ARM Core cache line fills or raster display memory access Cache line fills use quad word bursts and raster accesses use 16 word bursts The worst case is the raster which will hold the SDRAM controller for 20 AHB clocks Assuming a worst case system load where raster is getting 50 of the memory bandwidth and each raster burst in between is a cache line fil...

Page 777: ...DMAide signal deassertion is generated based on the contents of the Ultra DMA write FIFO If the FIFO contains four or more elements the DMAide signal deasserts Ultra DMA Read from IDE Controller The DMAide signal deassertion is generated based on an internal counter The DMAide signal will deassert if four DMA reads have occurred or if the FIFO is now empty which only occurs at the end of a non qua...

Page 778: ... this is not the case the DMA controller must be configured to time out based on the wait state table in Table 27 3 and Table 27 4 Quad word bursts are not allowed 27 2 7 3 2 Multi word DMA Follow the wait state number listed in the wait state table in Table 27 3 and Table 27 4 Quad word bursts are not allowed Table 27 3 Wait State Value for the DMA M2M Register Control PWSC Wait States Multi Word...

Page 779: ...ible if the Ultra DMA transfer size is quad word aligned 27 2 8 IDE Package Dependency The block uses the following external pins IDECS0n IDECS1n IDEDA DIORn DIOWn DMACKn DD IORDY INT 3 EGPIO 2 and EGPIO 15 27 2 8 1 System Configuration Constraints The following system configuration modes force the disabling of the IDE controller GPIOEonIDE GPIOFonIDE GPIOGonIDE GPIOHonIDE 27 2 8 2 Bus Bandwidth R...

Page 780: ...00A_0000 IDECtrl IDE Control Register 0x800A_0004 IDECfg IDE Configuration Register 0x800A_0008 IDEMDMAOp IDE MDMA Operation Register 0x800A_000C IDEUDMAOp IDE UDMA Operation Register 0x800A_0010 IDEDataOut IDE PIO Data Output Register 0x800A_0014 IDEDataIn IDE PIO Data Input Register 0x800A_0018 IDEMDMADataOut IDE MDMA Data Output Register 0x800A_001C IDEMDMADataIn IDE MDMA Data Input Register 0x...

Page 781: ... This signal comes in on the EGPIO 2 pin Read only INTRQ INTRQ pin input state This input comes from the INT 3 input pin and is routed to the Interrupt Controller Read only IORDY IORDY pin input state Read only IDECfg Address 0x800A_0004 Read Write Default 0x0000_0000 Definition IDE Configuration Register Bit Descriptions RSVD Reserved Unknown during read ignored during write IDEEN IDE master enab...

Page 782: ...s after a PIO write operation IDEMDMAOp Address 0x800A_0008 Read Write Default 0x0000_0000 Definition IDE MDMA Configuration Register Bit Descriptions RSVD Reserved Unknown during read ignored during write MEN Enable Multiword DMA operation 1 to start MDMA 0 to terminate MDMA by the host RWOP Read or write operation selection 0 Read 1 Write IDEUDMAOp Address 0x800A_000C Read Write 31 30 29 28 27 2...

Page 783: ...d Write Default 0x0000_0000 Definition In PIO mode write operation this register is the Output Data Registers containing the register contents or the data to be written to the device The register is driven onto the DD pins when DIOWn is low The register is both read write in this operation In MDMA and UDMA data out operations this register is an exact copy of the data in the output buffer to be tr...

Page 784: ...ster is read only in these operations Any write to this register is ignored Bit Descriptions IDEDD IDE input data in PIO read data in input buffer in MDMA and data at the head of input buffer in UDMA mode IDEMDMADataOut Address 0x800A_0018 Write Only should be written by the DMA controller only Default 0x0000_0000 Definition In MDMA data out operations this register contains the data in the output...

Page 785: ...ter by the DMA controller This register should only be addressed and read by the DMA controller A read by the host during MDMA data in operation will erroneously interfere with the MDMA state machine Any write is ignored Bit Descriptions IDEDD IDE input data in the input buffer in MDMA mode IDEUDMADataOut Address 0x800A_0020 Write Only should be written by the DMA controller only Default 0x0000_00...

Page 786: ...ad of the input buffer to be transferred by the DMA controller The data is read from this register by the DMA controller This register should only be addressed and read by the DMA controller A read by the host during UDMA data in operation will erroneously interfere with the UDMA state machine Any write is ignored Bit Descriptions IDEDD IDE input data at the head of the input buffer in UDMA mode I...

Page 787: ...address status Should be driven to 0x0 de asserted in UDMA HSHD HSTROBE during data out and HDMARDYn during data in status Driven by UDMA state machine STOP STOP during data out status Driven by UDMA state machine DM DMACKn both data out and data in status Driven by UDMA state machine DDOE DD bus output enable as controlled by UDMA state machine DMARQ Synchronized version of DMARQ input from devic...

Page 788: ...or RWPTR Reset UDMA write buffer pointer to 0 RWDR Reset UDMA write DMA request RROE Reset UDMA read data in error RRPTR Reset UDMA read buffer pointer to 0 RRDR Reset UDMA read DMA request IDEUDMAWrBufSts Address 0x800A_0030 Read Only Default 0x0000_0100 Definition Status register for UDMA write buffer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD...

Page 789: ... finishing UDMA operation IDEUDMARdBufSts Address 0x800A_0034 Read Only Default 0000_0100 Definition Status register for UDMA read buffer Bit Descriptions RSVD Reserved Unknown during read ignored during writes HPTR Head pointer in the read buffer TPTR Tail pointer in the read buffer EMPTY Read buffer empty status HOM Half or more entries in read buffer filled status NFULL Read buffer near full st...

Page 791: ... EEDAT pins It is a secondary controller for the ROW 7 0 COL 7 0 PCMCIA and IDE control pins There are two types of GPIOs standard and enhanced The enhanced GPIO called EGPIO have interrupt generation capability The GPIO block has eight ports named Port A through Port H Ports C D E G and H are standard GPIO ports Ports A B and F are enhanced GPIO ports Each GPIO port controls eight individual pins...

Page 792: ...rt C ROW 7 0 MUX_IO OE DATA EP Control Mux Controls Port D COL 7 0 MUX_IO OE DATA EP Control Mux Controls Port E MUX_IO OE DATA EP Control Mux Controls Port F VS2 MUX_IO OE DATA EP Control Mux Controls Port G DD 15 12 MUX_IO OE DATA EP Control Mux Controls Port H DD 7 0 MUX_IO OE DATA EP Control Mux Controls SLA 1 0 EEDAT EECLK IDEDA 2 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 IDECS0n IDECS1n DIORn RDLED ...

Page 793: ...and F interrupts Debouncing is implemented using a 2 bit shift register clocked by a 128 Hz clock There are seven additional registers for port A B and F GPIO Interrupt Enable registers GPIOAIntEn GPIOBIntEn GPIOFIntEn control which bits are to be configured as interrupts Setting a bit in this register configures the corresponding pin as an interrupt input GPIO Interrupt Type 1 registers GPIOAIntT...

Page 794: ...register 2 Set interrupt type by writing GPIOxINTTYPE1 2 register 3 Clear interrupt by writing to GPIOxEOI register 4 Enable interrupt by writing to GPIO Interrupt Enable register Figure 28 2 and Figure 28 3 illustrate the signal connections for GPIO and EGPIO Figure 28 2 Signal Connections Within the Standard GPIO Port Control Logic Ports C D E G H DDR OE 7 0 OE Standard GPIO Ports C D E G and H ...

Page 795: ...nputs Port E 1 0 bits are used for the LED outputs RDLED and GRLED respectively and are set to drive high Port G 3 2 bits are used for SLA 1 0 outputs and are set to drive low Port G 1 0 bits are used for EEDAT and EECLK respectively and are set up as inputs All interrupt control and debounce registers are cleared Enhanced GPIO Ports A B and F DDR OE 7 0 OE DR DATA DATA 7 0 EP 7 0 TISR OE to PRDAT...

Page 796: ...D is the Red LED pin 3 EECLK is the EEPROM clock pin 4 EEDAT is the EEPROM data pin 1 GRLED is the Green LED pin 2 RDLED is the Red LED pin 3 EECLK is the EEPROM clock pin Table 28 1 EP9301 and EP9302 GPIO Port to Pin Map Pin Name Default Function EGPIO 7 0 Port A EGPIO 15 8 Port B GRLED1 Port E0 RDLED2 Port E1 EECLK3 Port G0 EEDAT4 Port G1 Table 28 2 EP9307 GPIO Port to Pin Map Pin Name Default F...

Page 797: ...nction in GonIDE Mode Function in HonIDE Mode EGPIO 7 0 Port A Port A Port A Port A Port A EGPIO 15 8 Port B Port B Port B Port B Port B GRLED3 Port E0 Port E0 Port E0 Port E0 Port E0 RDLED4 Port E1 Port E1 Port E1 Port E1 Port E1 EECLK5 Port G0 Port G0 Port G0 Port G0 Port G0 EEDAT6 Port G1 Port G1 Port G1 Port G1 Port G1 SLA 1 0 Port G3 2 Port G3 2 Port G3 2 Port G3 2 Port G3 2 ROW 7 0 7 ROW 7 0...

Page 798: ...Port E0 RDLED6 Port E1 Port E1 Port E1 Port E1 Port E1 VS22 Port F7 Port F7 Port F7 Port F7 Port F7 READY2 Port F6 Port F6 Port F6 Port F6 Port F6 VS12 Port F5 Port F5 Port F5 Port F5 Port F5 MCBVD 2 1 2 Port F4 3 Port F4 3 Port F4 3 Port F4 3 Port F4 3 MCD 2 1 2 Port F2 1 Port F2 1 Port F2 1 Port F2 1 Port F2 1 WP2 Port F0 Port F0 Port F0 Port F0 Port F0 EECLK7 Port G0 Port G0 Port G0 Port G0 Por...

Page 799: ... TonG maps TENn the RS485 transmit enable output onto EGPIO 3 Both HC3EN and HC1EN map the synchronous HDLC clock onto EGPIO 3 Some GPIO signals are used as inputs by other functional blocks EGPIO 2 1 are routed to the DMA controller to allow for external DMA requests IDE interface input signals DMARQ and DASPn are EGPIO 2 and EGPIO 15 respectively 28 2 Registers Table 28 5 GPIO Register Address M...

Page 800: ...efault Register Descriptions PxDR Address 0x8084_0050 GPIOFIntType2 R W GPIOFIntType2 0x00 0x8084_0054 Reserved Read undefined Write Only GPIOFEOI 0x00 0x8084_0058 GPIOFIntEn R W GPIOFIntEn 0x00 0x8084_005C IntStsF Read only 0x00 0x8084_0060 RawIntStsF Read only Note 3 0x8084_0064 GPIOFDB R W GPIOFDB 0x00 0x8084_0090 GPIOAIntType1 R W GPIOAIntType1 0x00 0x8084_0094 GPIOAIntType2 R W GPIOAIntType2 ...

Page 801: ... a system reset X stands for a letter A through H Bit Descriptions RSVD Reserved Unknown During Read PxDATA Port x 8 bit data PxDDR Address PADDR 0x8084_0010 Read Write PBDDR 0x8084_0014 Read Write PCDDR 0x8084_0018 Read Write PDDDR 0x8084_001C Read Write PEDDR 0x8084_0024 Read Write PFDDR 0x8084_0034 Read Write PGDDR 0x8084_003C Read Write PHDDR 0x8084_0044 Read Write Definition Port x Data Direc...

Page 802: ...fault on reset to a bit in the register will configure that bit on port A B F as a normal GPIO port and the interrupt output corresponding to that bit will be zeroed The user can read the inputs on port A B F in either mode via the PxDR The interrupt type is controlled by the GPIOxINTTYPE1 2 registers described in the following sections Bit Descriptions RSVD Reserved Unknown During Read PxINT Port...

Page 803: ...2 0x8084_0050 Read Write Definition The GPIOxINTTYPE2 registers controls the type of edge level sensitive interrupt that can occur on the bits in Ports A B F The interrupt is rising edge or high level sensitive if a 1 is written to the corresponding bit in GPIOxINTTYPE2 and falling edge or low level sensitive if a 0 is written to the corresponding bit in GPIOxINTTYPE2 The user must make sure that ...

Page 804: ... be a write to this location in order to clear the interrupt so that subsequent interrupts on the same line are not missed Bit Descriptions RSVD Reserved Unknown During Read PxINTC Clears Interrupts GPIOxDB Address GPIOADB 0x8084_00A8 Read Write GPIOBDB 0x8084_00C4 Read Write GPIOFDB 0x8084_0064 Read Write Definition For each port if interrupts are enabled it is possible to debounce the input sign...

Page 805: ...he interrupt is level sensitive active high it reflects the pin value If level sensitive active low it reflects the inverse of the pin value If the interrupt is edge triggered the bit latches a one whenever the proper level change occurs How a bit is cleared also depends on the interrupt type When an interrupt is level sensitive it is cleared when not asserted When edge triggered it is cleared by ...

Page 806: ...his register reports the same value as the RawIntStsX register for each bit whose corresponding interrupt is enabled Bits whose corresponding interrupt is not enabled report 0 Bit Descriptions RSVD Reserved Unknown During Read PxINTS Masked Interrupt Status EEDrive Address 0x8084_00C8 Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD DATOD C...

Page 807: ...he EECLK and EEDAT pins When set the corresponding pin is open drain so that the pin will require an external pull up When clear the corresponding pin is a normal CMOS driver DATOD controls the EEDAT pin CLKOD controls the EECLK pin Bit Descriptions RSVD Reserved Unknown During Read DATOD Defines the EEDAT pin output driver CLKOD Defines the EECLK pin output driver ...

Page 809: ...re Digital Music Initiative and allows for protection of object code as well as content 29 2 Features Key features include 256 bits of laser fuse for permanent IDs and passwords Security boot firmware and private passwords are invisible except when the IC is locked Each instantiation of the system software may be uniquely encoded and protected using the private ID Multiple security vendors can co ...

Page 810: ...l information regarding security features Register Descriptions ExtensionID Address 0x8083_2714 Read Only Definition This register contains the PartID for EP93XX processors Bit Descriptions RSVD Reserved Unknown During Read PartID Identification number for each type of EP93XX processors See the respective EP93xx processor data sheet to determine the PARTID for a specific EP93xx processor Table 29 ...

Page 811: ...hat is a start address and the length of the buffer in bytes CODEC Coder Decoder CRC Cyclic Redundancy Check DAC Digital to Analog Converter DMA Direct Memory Access EEPROM Electronically Erasable Programmable Read Only Memory FIQ Fast Interrupt Request FIR Fast Infrared FLASH FLASH memory GPIO General Purpose Input Output HDLC High level Data Link Control I2C See I2 S I2S Inter IC Sound also know...

Page 812: ... Return to zero Inverted SDLC Synchronous Data Link Control SDMI Secure Digital Music Initiative SDRAM Synchronous Dynamic Random Access Memory SIR Slow Infrared SPI Serial Peripheral Interface Also known as SSP Synchronous Serial Interface supporting the Motorola SPI format SRAM Static Random Access Memory Syscon System control registers TFT Thin Film Transistor TLB Translation Lookaside Buffer T...

Page 813: ...discussion of that register Table 31 1 EP93xx Register List Register Name Page Number AC97RISRx 22 13 GrySclLUTB 7 73 AC97DRx 22 6 AC97EOI 22 20 AC97GCIS 22 24 AC97GCR 22 21 AC97GIS 22 19 AC97IEx 22 15 AC97IM 22 20 AC97ISRx 22 14 AC97Reset 22 22 AC97RGIS 22 18 AC97RXCRx 22 7 AC97S12Data 22 17 AC97S1Data 22 15 AC97S2Data 22 16 AC97SRx 22 12 AC97SYNC 22 23 AC97TXCRx 22 10 ACRate 7 56 AFP 9 52 APBWai...

Page 814: ...4 BootSts 13 17 Brightness 7 50 BusMstrArb 5 23 CHIP_ID 5 33 ClkSet1 5 18 ClkSet2 5 20 ColorLUT 7 77 CONTROL 10 22 CONTROL 10 31 CURRENTx 10 30 CursorAdrReset 7 67 CursorAdrStart 7 66 CursorBlinkColor1 7 69 CursorBlinkColor2 7 69 CursorBlinkRateCtrl 7 72 CursorColor1 7 69 CursorColor2 7 69 CursorDScanLHYLoc 7 71 CursorSize 7 68 CursorXYLoc 7 70 DAR_BASEx 10 43 DAR_CURRENTx 10 44 DESTLINELENGTH 8 2...

Page 815: ...R 17 36 FISR 17 35 GlConfig 13 14 GlIntFrc 9 64 GlIntMsk 9 63 GlIntROSts 9 64 GlIntSts 9 62 GPIOxDB 28 14 GPIOxEOI 28 14 GPIOxIntEn 28 12 GPIOxIntType1 28 12 GPIOxIntType2 28 13 GrySclLUTG 7 73 GrySclLUTR 7 73 GT 9 49 HActiveStrtStop 7 43 HashTbl 9 54 HBlankStrtStop 7 44 HcBulkCurrentED 11 23 HcBulkHeadED 11 22 HcCommandStatus 11 15 HcControl 11 12 HcControlCurrentED 11 22 HcControlHeadED 11 21 Ta...

Page 816: ...27 HcPeriodCurrentED 11 20 HcPeriodicStart 11 26 HcRevision 11 12 HcRhDescriptorA 11 28 HcRhDescriptorB 11 29 HcRhPortStatusx 11 32 HcRhStatus 11 30 HSigStrtStop 7 80 HSyncStrtStop 7 42 I2SClkDiv 5 31 I2SGlCtrl 21 31 I2SGlSts 21 29 I2SRX0En 21 24 I2SRX0Lft 21 19 I2SRX0Rt 21 20 I2SRX1En 21 24 I2SRX1Lft 21 20 I2SRX1Rt 21 21 I2SRX2En 21 25 I2SRX2Lft 21 21 I2SRX2Rt 21 22 I2SRXClkCfg 21 27 I2SRXCtrl 21...

Page 817: ...lData 21 16 I2STXWrdLen 21 17 IDECfg 27 11 IDECtrl 27 10 IDEDataIn 27 14 IDEDataOut 27 13 IDEMDMADataIn 27 15 IDEMDMADataOut 27 14 IDEMDMAOp 27 12 IDEUDMADataIn 27 16 IDEUDMADataOut 27 15 IDEUDMADebug 27 18 IDEUDMAOp 27 12 IDEUDMARdBufSts 27 19 IDEUDMASts 27 16 IDEUDMAWrBufSts 27 18 IndAd 9 53 IntEn 9 57 INTERRUPT 10 35 INTERRUPT 10 25 IntStsP IntStsC 9 60 IntStsX 28 15 IrAdrMatchVal 17 25 IrCtrl ...

Page 818: ...ry 7 49 LINEINC 8 36 LINEINIT 8 36 LineLength 7 47 LINEPATTRN 8 37 LUTSwCtrl 7 76 MAXCNTx 10 29 MaxFrmLen 9 91 MIICmd 9 65 MIIData 9 66 MIIR 17 34 MIISts 9 66 MIMR 17 33 MIRClkDiv 5 30 MISR 17 32 ParllIfIn 7 61 ParllIfOut 7 60 PattrnMask 7 65 PCAttribute 12 13 PCCommon 12 14 PCIO 12 15 PCMCIACtrl 12 17 PixelMode 7 57 PPALLOC 10 23 PWMxDutyCycle 24 4 PWMxEn 24 5 PWMxInvert 24 5 Table 31 1 EP93xx Re...

Page 819: ...eive Status First Word 9 18 Receive Status Second Word 9 20 RefrshTimr 13 16 REMAIN 10 28 RTCCtrl 20 6 RTCData 20 4 RTCLoad 20 6 RTCMatch 20 5 RTCSts 20 5 RTCSWComp 20 7 RXBCA 9 74 RXBufThrshld 9 85 RXCtl 9 41 RXDCurAdd 9 73 RXDEnq 9 74 RXDQBAdd 9 71 RXDQBLen 9 72 RXDQCurLen 9 72 RXDThrshld 9 89 RXHdrLen 9 78 RXMissCnt 9 55 RXRuntCnt 9 56 RXStsEnq 9 78 RXStsQBAdd 9 75 RXStsQBLen 9 76 RXStsQCurAdd ...

Page 820: ...0 12 10 SRCLINELENGTH 8 26 SRCPIXELSTRT 8 23 SSPCPSR 23 18 SSPCR0 23 13 SSPCR1 23 14 SSPDR 23 16 SSPIIR SSPICR 23 18 SSPSR 23 17 Standby and Halt 5 17 STATUS 10 26 STATUS 10 37 STFClr 5 18 SysCfg P 4 SysCfg 5 34 SysSWLock 5 35 TEOI 5 17 TestCtl 9 57 Timer1Clear 18 5 Timer1Control 18 6 Timer1Load 18 3 Timer1Value 18 4 Timer2Clear 18 5 Timer2Control 18 6 Timer2Load 18 3 Timer2Value 18 4 Timer3Clear ...

Page 821: ...arge TSXSample TSYSample TSDirect TSDetect 25 20 TSSetup 25 17 TSSetup2 25 22 TSSWLock 25 21 TSXYMaxMin 25 19 TSXYResult 25 19 TXBufThrshld 9 86 TXCollCnt 9 55 TXCtl 9 44 TXDEnq 9 82 TXDQBAdd 9 79 TXDQBLen 9 80 TXDQCurAdd 9 81 TXDQCurLen 9 80 TXDThrshld 9 90 TXStsQBAdd 9 82 TXStsQBLen 9 83 TXStsQCurAdd 9 84 TXStsQCurLen 9 84 TXStsThrshld 9 88 UART1Ctrl 14 22 UART1Data 14 17 UART1DMACtrl 14 25 UART...

Page 822: ...T2DMACtrl 15 16 UART2Flag 15 13 UART2IntIDIntClr 15 14 UART2IrLowPwrCntr 15 15 UART2LinCtrlHigh 15 9 UART2LinCtrlLow 15 11 UART2LinCtrlMid 15 10 UART2RXSts 15 8 UART2TMR 15 17 UART3Ctrl 16 8 UART3Data 16 3 UART3DMACtrl 16 11 UART3Flag 16 9 UART3HDLCAddMask 16 16 UART3HDLCAddMtchVal 16 16 UART3HDLCCtrl 16 13 UART3HDLCRXInfoBuf 16 17 UART3HDLCSts 16 18 UART3IntIDIntClr 16 10 UART3LinCtrlHigh 16 5 UA...

Page 823: ...VICxProtection 6 13 VICxRawIntr 6 10 VICxSoftInt 6 12 VICxSoftIntClear 6 13 VICxVectAdd12 6 16 VICxVectAdd9 6 16 VICxVectAddr 6 14 VICxVectAddr0 6 15 VICxVectAddr1 6 15 VICxVectAddr10 6 16 VICxVectAddr11 6 16 VICxVectAddr13 6 16 VICxVectAddr14 6 16 VICxVectAddr15 6 16 VICxVectAddr2 6 15 VICxVectAddr3 6 15 VICxVectAddr4 6 15 VICxVectAddr5 6 15 VICxVectAddr6 6 15 VICxVectAddr7 6 16 VICxVectAddr8 6 1...

Page 824: ...Cntl2 6 17 VICxVectCntl3 6 17 VICxVectCntl4 6 17 VICxVectCntl5 6 17 VICxVectCntl6 6 17 VICxVectCntl7 6 17 VICxVectCntl8 6 17 VICxVectCntl9 6 17 VidClkDiv 5 29 VideoAttribs 7 51 VidScrnHPage 7 46 VidScrnPage 7 46 VidSigCtrl 7 78 VidSigRsltVal 7 77 VLineStep 7 48 VLinesTotal 7 38 VSigStrtStop 7 79 VSyncStrtStop 7 38 Watchdog 19 3 WDStatus 19 5 Table 31 1 EP93xx Register List Register Name Page Numbe...

Page 825: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Cirrus Logic EP9315 CBZ EP9315 IBZ ...

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