•
Quad Gigabit Ethernet (QGLC)
•
10 Gigabit Ethernet Line Card (XGLC)
Line Card Rules
The following engineering rules apply to the Fast Ethernet 10/100, Gigabit Ethernet 1000, Quad Gigabit
Ethernet and 10 Gigabit Ethernet line cards:
•
Give all logical interfaces a unique name to identify the interface from others in the same context. Logical
interfaces in different contexts may have the same name.
•
A single physical port can support multiple logical interfaces when you configure VLAN tags for that
physical port. You can use VLAN tagging to bind a single physical port to multiple logical interfaces
that reside in different contexts.
•
Assign all logical interfaces a valid IP address and subnet.
•
Give each logical interface within a context a unique IP address(es). Logical interfaces in different
contexts can have the same IP address(es).
•
If multi-homing is supported on the network, you can assign all logical interfaces a single primary
IP address and up to 16 secondary IP addresses.
•
You can configure a logical interface in only one context, but you can configure multiple interfaces (up
to 512 Ethernet or 1,024 ATM) in a single context.
•
You can apply a maximum of 128 access control list (ACL) rules to a single logical interface.
•
All ports are identified by their <slot#>/<port#>.
•
Each physical port on a Gigabit Ethernet 1000 or Quad Gigabit line card may contain up to a maximum
of 1,024 VLAN tags.
•
Each physical port on an Fast Ethernet 10/100 Line card may contain up to a maximum of 256 VLAN
tags.
•
The total number of VLANs untagged and/or tagged on each Fast Ethernet 10/100 Line Card must not
exceed 1025 (8 un 1,017 tagged).
•
A logical interface is limited to using a single VLAN or ATM PVC on a single physical port, identified
by its <cardslot#/port#>.
•
When using redundant (standby) line cards:
•
You must configure the active line card only. In the event of a failover, all relevant information
(including the IP address) is transferred to the standby line card.
•
Half-height line cards must installed in the upper and lower chassis slots behind a sa packet processor
card must be of the same type: FELC/FLC2,GELC/GLC2, or QGLC line cards.
ASR 5000 System Administration Guide, StarOS Release 21.1
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Engineering Rules
Line Card Rules
Summary of Contents for ASR 5000
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