Configuring Cisco Multimode G.SHDSL EFM/ATM in Cisco ISR G2
Troubleshooting Cisco G.SHDSL EFM/ATM
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Configuring Cisco Multimode G.SHDSL EFM/ATM in Cisco ISR G2
HWICQueueBaseExtension 0x00
GDF Ring 0 Registers:
HWICQueueConfig Register 0x0007 HWICQueueBase 0x1DAD
TXQueueTailBase Register 0x4048
TxQueueBase 0x08 TxQueueTail 0x09
TxQueueSize 0x40 TxQueueHead 0x09
RxQueueHeadBase Register 0x4800
RxQueueBase 0x09 RxQueueHead 0x00
RxQueueSize 0x40 RxQueueTail 0x00
RxBufferSize 0x060C RxQueueHighWaterMark 0x00
RxQueueLowWaterMark 0x00
DMAOffsetExtension 0x00
DMAOffset 0x0000 DMAWindow 0x0000
HWICSuspResDbg Register 0x0000 HWICArbConfig Register 0x000F
GDF Ring 1 Registers:
HWICQueueConfig Register 0x0000 HWICQueueBase 0x0000
TXQueueTailBase Register 0x0000
TxQueueBase 0x00 TxQueueTail 0x00
TxQueueSize 0x00 TxQueueHead 0x00
RxQueueHeadBase Register 0x0000
RxQueueBase 0x00 RxQueueHead 0x00
RxQueueSize 0x00 RxQueueTail 0x00
RxBufferSize 0x0000 RxQueueHighWaterMark 0x00
RxQueueLowWaterMark 0x00
GDF Ring 2 Registers:
HWICQueueConfig Register 0x0000 HWICQueueBase 0x0000
TXQueueTailBase Register 0x0000
TxQueueBase 0x00 TxQueueTail 0x00
TxQueueSize 0x00 TxQueueHead 0x00
RxQueueHeadBase Register 0x0000
RxQueueBase 0x00 RxQueueHead 0x00
RxQueueSize 0x00 RxQueueTail 0x00
RxBufferSize 0x0000 RxQueueHighWaterMark 0x00
RxQueueLowWaterMark 0x00
GDF Ring 3 Registers:
HWICQueueConfig Register 0x0000 HWICQueueBase 0x0000
TXQueueTailBase Register 0x0000
TxQueueBase 0x00 TxQueueTail 0x00
TxQueueSize 0x00 TxQueueHead 0x00
RxQueueHeadBase Register 0x0000
RxQueueBase 0x00 RxQueueHead 0x00
RxQueueSize 0x00 RxQueueTail 0x00
RxBufferSize 0x0000 RxQueueHighWaterMark 0x00
RxQueueLowWaterMark 0x00
GDF Error Interrupt Enable Register (0x0000):
GDF Rx Resume Error Int 0x00 GDF Rx Done Error Int 0x00
GDF Tx First/Last Error Int 0x00 GDF Tx Done Error Int 0x00
GDF Error Interrupt Event Register (0x0000):
GDF Rx Resume Error Event 0x00 GDF Rx Done Error Event 0x00
GDF Tx First/Last Error Event 0x00 GDF Tx Done Error Event 0x00
******* HWIC Common Registers at EC600000 *******
HWIC ID: 0x2
HWIC Revision: 0x0
HWIC Status: 0x0
HWIC DDR TXCRC:0x0
HWIC Control: 0xC000
DDR Enable 1 Software Reset 1
Interrupt Module Reset 0 GDF Module Reset 0
DMA Module Reset 0 Flow Control Reset 0
IRQ2 Global Int Mask 0 IRQ1 Global Int Mask 0
DDR TXCRC Int Mask 0 DDR TXClk Loss Int Mask 0
TX Fifo Overrun Int Mask 0
HWIC Interrupt Event: 0x0