16-110
Cisco ONS 15454 DWDM Installation and Operations Guide, R6.0
April 2006
Chapter 16 Card Reference
16.8.6 MXP_MR_2.5G and MXPP_MR_2.5G Cards
Figure 16-66
MXP_MR_2.5G and MXPP_MR_2.5G Faceplates
16.8.6.2 Block Diagram
shows a block diagram of the MXP_MR_2.5G card. The card has eight SFP client
interfaces. Ports 1 and 2 can be used for GE, FC, or FICON. Ports 3 through 8 are for future use. There
are two SERDES blocks dedicated to the high-speed interfaces (GE, FC, and FICON) and two SERDES
blocks for future interfaces. A field programmable gate array (FPGA) is provided to support different
configurations for different modes of operation. This FPGA has a Universal Test and Operations
Physical Interface for ATM (UTOPIA) interface. A transceiver add-drop multiplexer (TADM) chip
MXP_MR_2.5G
MXPP_MR_2.5G
124077
MXP
MR
2.5G
15xx.xx
15xx.xx
FAIL
ACT/STBY
SF
MXPP
MR
2.5G
15xx.xx
15xx.xx
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
D
WDMA
D
WDMB
FAIL
ACT/STBY
SF
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
D
WDM
RX
TX
Summary of Contents for ONS 15454 DWDM
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