4-14
PA-MC-2T3+ Multi-Channel T3 Port Adapter Installation and Configuration
OL-3526-05
Chapter 4 Configuring Unchannelized mode for the Cisco PA-MC-2T3+
Configuring an Unchannelized T3 Link
Viewing the Results of a BER Test
You can view the results of a BER test using the controller command:
show controllers T3
slot/port-adapter/t3-port for Cisco 7500 series routers
show controllers T3
slot/t3-port for Cisco 7200 series routers
show controllers T3
slot/t3-port for Cisco 7401ASR routers
You can view the results of a BER test at the following times:
•
After you terminate the test using the
no bert
command
•
After the test runs completely
•
Anytime during the test (in real time)
Examples follow:
•
The example that follows is for a port adapter on a VIP in interface processor slot 1:
Router#
show controller T3 1/0/0
T3 1/0/0 is up. Hardware is 2CT3+ single wide port adapter
CT3 H/W Version: 0.1.1, CT3 ROM Version: 0.95, CT3 F/W Version: 1.4.4
FREEDM version: 1, reset 0
Applique type is Subrate T3
No alarms detected.
MDL transmission is disabled
FEAC code received: No code is being received
Framing is C-BIT Parity, Line Code is B3ZS, Clock Source is Internal
Rx throttle total 0, equipment customer loopback
Data in current interval (9 seconds elapsed):
0 Line Code Violations, 0 P-bit Coding Violation
0 C-bit Coding Violation, 0 P-bit Err Secs
0 P-bit Severely Err Secs, 0 Severely Err Framing Secs
9 Unavailable Secs, 0 Line Errored Secs
0 C-bit Errored Secs, 0 C-bit Severely Errored Secs
Data in Interval 1:
0 Line Code Violations, 0 P-bit Coding Violation
0 C-bit Coding Violation, 0 P-bit Err Secs
0 P-bit Severely Err Secs, 0 Severely Err Framing Secs
0 Unavailable Secs, 0 Line Errored Secs
0 C-bit Errored Secs, 0 C-bit Severely Errored Secs
Data in Interval 2:
0 Line Code Violations, 0 P-bit Coding Violation
0 C-bit Coding Violation, 0 P-bit Err Secs
0 P-bit Severely Err Secs, 0 Severely Err Framing Secs
0 Unavailable Secs, 0 Line Errored Secs
0 C-bit Errored Secs, 0 C-bit Severely Errored Secs
Data in Interval 3:
0 Line Code Violations, 0 P-bit Coding Violation
0 C-bit Coding Violation, 0 P-bit Err Secs
0 P-bit Severely Err Secs, 0 Severely Err Framing Secs
0 Unavailable Secs, 0 Line Errored Secs
0 C-bit Errored Secs, 0 C-bit Severely Errored Secs
Data in Interval 4:
0 Line Code Violations, 0 P-bit Coding Violation
0 C-bit Coding Violation, 0 P-bit Err Secs
0 P-bit Severely Err Secs, 0 Severely Err Framing Secs
0 Unavailable Secs, 0 Line Errored Secs
0 C-bit Errored Secs, 0 C-bit Severely Errored Secs
Data in Interval 5:
0 Line Code Violations, 0 P-bit Coding Violation
