Sheet 12 of 43
HDMI, CRT
Schematic Diagrams
HDMI, CRT B - 13
B.Schematic Diagrams
HDMI, CRT
R803
* 2.2K_04
C125
0. 1u_10V_X7R_04
R396
*499_1%_04
HDMI PORT
C138
0. 1u_10V_X7R_04
R804
*4.7K_04
5VS
11,13,19,20,25, 29, 30, 31, 36, 37
3.3VS
3, 9, 10,11,13,14,15,16,17,18,19,20,23,24,25,27, 28, 29, 30, 31, 36
R734
*20m il_04
R735
*20m il_04
C127
0. 1u_10V_X7R_04
3.3VS
Parade PS8171
C675
*2.2u_6. 3V_X5R_06
CEXT
CEXT
C141
0. 1u_10V_X7R_04
R805
*0_04
HD MIB_D1BN
HD MIB_D0BN
HD MIB_D1BP
HD MIB_D2BP
HD MIB_D2BN
HD MIB_CLKBP
HD MIB_D0BP
HDMIB_DATA1P
HDMIB_DATA0P
HDMIB_EXT1_SCL
HDMIB_DATA1N
HDMIB_DATA0N
P IN 4 9 =G N D
HDMI_HPD-C
HDMIB_EXT1_SDA
HDMIB_CLOCKN
HDMIB_CLOCKP
HDMIB_DATA2P
HDMIB_DATA2N
FOR INTEL GRAPHIC
HD MI_CTRLCLK
HD MI_CTRLDATA
HDMI_CTRLD ATA
16
HDMI_CTRLC LK
16
W/ level shift: 100K
W/O level shift: 20K
PORTC_H PD
R55
20K_1%_04
POR TC_HPD
16
R737
*20m il_04
R736
*20m il_04
H DMIB_D1BN_C
16
H DMIB_D2BN_C
16
H DMIB_D1BP_C
16
H DMIB_D2BP_C
16
H DMIB_CLKBN_C
16
H DMIB_D0BN_C
16
H DMIB_CLKBP_C
16
H DMIB_D0BP_C
16
J_CR T1
108AH15FST04A1CC
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
GN
D2
G
ND1
RED
DC C_EN#
DDCDATA
DDCLK
R54
*4. 7K_04
VSY N C
HSY N C
GRN
BLUE
W/O level shift
C
7
100
0
p
_50V
_
X
7R
_0
4
C
1
5
100
0p
_50V
_
X
7R
_0
4
C
9
220
p_
50V
_N
P
O
_04
C
11
22
0p_
5
0
V
_N
P
O
_04
C
17
*
10p_
50
V
_N
P
O
_0
4
C
18
10p_
50
V
_N
P
O
_0
4
C
1
4
10p_
5
0
V
_N
P
O
_04
C
13
*1
0p_
5
0
V
_N
P
O
_04
C
19
10
p_50
V
_
N
P
O
_0
4
C
21
*10
p
_
50V
_
N
P
O
_
04
.
L7
0_04
6-19-31001-264
.
L4
0_04
.
L6
0_04
C
16
22p
_50
V
_
N
P
O
_
0
4
C
12
22p_
50
V
_N
P
O
_0
4
C
20
2
2
p_50
V
_
N
P
O
_0
4
.
L8
F CM1005MF -600T01
.
L5
F CM1005MF -600T01
.
L3
F CM1005MF -600T01
DAC_RED
16
DAC_BLUE
16
DAC_GREEN
16
R
1
4
1
50_1
%_
0
4
R
13
150
_
1
%
_04
R
15
15
0_1
%
_04
DDCBUF: DDC Active Buffer enable and setting, 3 level CMOS input,
internal pull-down at ~ 500k ohm
DDCBUF=LOW: No DDC active buffer, passive DDC level shifting
DDCBUF=High: Active DDC bufer enable, setting 1
DDCBUF=MID: Active DDC bufer enable, setting 2
6-20-14X30-015
U5
* PS8171
IN _D1+
39
IN _D1-
38
IN _D2+
42
IN _D2-
41
IN _D3+
45
IN _D3-
44
IN _D4+
48
IN _D4-
47
SCL
9
SDA
8
HPD/ HPDX
7
OE#
25
DCC_EN #
32
CEXT/RT_EN#
10
PEQ/ PC0
3
PI O/PC1
4
REXT
6
EMI 0/ GND[ 6]
27
PRE/ QE_2
35
DDCBUF /OE_1
34
OUT_D 1+
22
OUT_D1-
23
OUT_D 2+
19
OUT_D2-
20
OUT_D 3+
16
OUT_D3-
17
OUT_D 4+
13
OUT_D4-
14
SC L_SI NK
28
SDA_SI NK
29
HPD_SI NK
30
VCC [1]
2
APD/ VCC[2]
11
VCC [3]
15
VCC [4]
21
VCC [5]
26
EMI 1/ VCC[6]
33
VCC [7]
40
VCC [8]
46
ASQ0/GND [1]
1
GND [2]
5
ASQ1/GND [3]
12
GND [4]
18
GND [5]
24
GND [7]
31
GND [8]
36
GND [9]
37
GND[ 10]
43
GN
D
49
R658
1M_04
HD MI B_EXT1_SCL
HD MI _HPD-C
PORTC _HPD
Q55
MTN7002ZHS3
G
D
S
HDMI_CTRLCLK
HD MI B_EXT1_SDA
R656
2. 2K_04
Q54
MTN 7002ZHS3
G
D
S
3.3VS
Q53
MTN7002ZHS3
G
D
S
R657
2. 2K_04
HDMI_CTRLDATA
HD MIB_CLKBN
HDMIB_EXT1_SDA
RD1
*BAV99 RECTI FIER
A
C
AC
HDMI_HPD-C
RD3
*BAV99 RECTIF IER
A
C
AC
RD2
*BAV99 RECTIF IER
A
C
AC
For ESD
HDMIB_EXT1_SCL
R403
2.
2
K
_0
4
R404
2.2
K
_
0
4
5VS_HDMI
PEQ
PIO
C137
0. 1u_10V_X7R_04
HDMI B_D2BP_M
HDMI B_C LOCKN
HDMI B_C LOCKP
HDMI B_CLKBN_M
HDMI B_CLKBP_M
H DMIB_D0BN
H DMIB_D0BP
HDMI B_D1BN_M
HDMI B_D1BP_M
HDMI B_D2BN_M
RN 21
*0_8P4R_04_SHORT
1
2
3
4
5
6
7
8
HDMI B_D0BP_M
R N20
*0_8P4R _04_SHORT
1
2
3
4
5
6
7
8
HDMI B_D0BN_M
HDMI B_D ATA2P
H DMIB_D1BN
H DMIB_D1BP
H DMIB_D2BN
H DMIB_D2BP
HDMI B_D ATA0P
H DMIB_CLKBN
H DMIB_CLKBP
HDMI B_D ATA1N
HDMI B_D ATA1P
HDMI B_D ATA2N
RN 23
*0_8P4R_04_SHORT
1
2
3
4
5
6
7
8
HDMI B_D ATA0N
RN22
*0_8P4R_04_SHORT
1
2
3
4
5
6
7
8
5VS
W/O level shift
3.3VS
R6
6
5
6
8
0_04
R
666
680_
04
R6
6
3
6
8
0_0
4
R
664
680
_04
TMDS_DATA1#
TMDS_DATA0
Q56
MTN7002ZHS3
G
D
S
W/O level shift
5VS_HDMI _I N
HDMIB_EXT1_SCL
HDMI_CEC
HDMIB_EXT1_SDA
HDMI_HPD-C
J_HDMI 1
C12817-119A5-L
SH IELD 2
2
TMDS DATA1+
4
TMDS DATA1-
6
SH IELD 0
8
TMDS CLOCK+
10
TMDS CLOCK-
12
RESERVED
14
SD A
16
+5V
18
TMDS DATA2+
1
TMDS DATA2-
3
SHI ELD1
5
TMDS DATA0+
7
TMDS DATA0-
9
C LK SHI ELD
11
CEC
13
SCL
15
DDC/CEC GND
17
H OT PLUG DETECT
19
GN
D
GND
1
GN
D
GN
D
2
GN
D
G
ND3
GN
D
GN
D
4
C349
10u_10V_Y 5V_08
HDMIB_DATA0P
TMDS_DATA1
HDMIB_DATA0N
3. 3VS
5VS_HDMI
HDMIB_DATA2N
C31
*0.1u_16V_Y 5V_04
C30
*0.1u_16V_Y 5V_04
HDMIB_DATA2P
TMDS_CLOCK#
C339
* 0.1u_16V_Y 5V_04
C348
10u_10V_Y 5V_08
C340
* 0.1u_16V_Y 5V_04
C338
*0.1u_16V_Y 5V_04
TMDS_CLOCK
HMDI _I NTEL
TMDS_DATA2#
R401
1_04
HMD I_IN TEL
APD: Automatic power down managementl, 3 level CMOS input,
internal pull-up at ~ 500k ohm
APD=LOW: Automatic power down disable
APD=High: Automatic power down enable
APD=MID: Reserved
EMI0,EMI1: EMI reduction and filter setting, 3 level CMOS input,
EMI1 internal pull-up at ~ 500k ohm
EMI0 internal pull-down at ~ 500k ohm
[EMI1,EMI0]=HL: No EMI reduction
EMI0=High: Increased rise/fall time
MID, Increased rise/fall time,2nd
EMI1=LOW: EMI filter setting 1
MID: Reserved
TMDS_DATA2
R
661
680
_04
R6
6
2
6
8
0_04
R
659
68
0_04
R6
6
0
680_
0
4
TMDS_C LOCK
TMDS_C LOCK#
TMDS_D ATA1#
HDMIB_D ATA1N
HDMIB_D ATA1P
HDMIB_C LOCKN
HDMIB_C LOCKP
TMDS_D ATA1
TMDS_DATA0#
R373
33_04
R372
33_04
CRT PORT
3. 3VS
DDCLK
U 33
TPD7S019
VCC_SYNC
1
VCC_VID EO
2
VIDEO_1
3
VIDEO_2
4
VIDEO_3
5
GND
6
VCC_D DC
7
BY P
8
DDC_OU T1
9
DDC_I N1
10
DDC_I N2
11
DDC_OU T2
12
SY NC_IN1
13
SY NC_OU T1
14
SY NC_IN2
15
SY NC_OU T2
16
C3
1
1
0
.2
2
u
_10V
_Y
5
V
_0
4
C3
1
2
0.
2
2u_1
0V
_Y
5V
_
04
C3
1
3
0.
2
2u_
10V
_Y
5
V
_04
3.3VS
3.3VS
5VS_CRT
CRT_H SY NC
DDCD ATA
RED
BLU E
GRN
HSY N C
VSY NC
CRT_VSY NC
DAC_VSY NC
16
DAC_H SY NC
16
C140
0. 1u_10V_X7R_04
DAC_DDCACLK
16
DAC_DDCADATA
16
D26
RB751S-40C2
A
C
RN1
2. 2K_8P4R_04
8
1
7
2
6
5
3
4
5VS
C124
0. 1u_10V_X7R_04
3. 3VS
R731
*20m il_04
R730
*20m il_04
R68
*0_04
R732
*20m il_04
D30
RB551V-30S2
A
C
R733
*20m il_04
OE#
C126
0. 1u_10V_X7R_04
EMI 1
APD
3.3VS
PEQ
R781
*4.7K_04
PIO
R784
*4.7K_04
R783
*4.7K_04
R785
*4.7K_04
R790
*4.7K_04
R788
*4.7K_04
R787
*4.7K_04
R789
*4.7K_04
R782
*4.7K_04
R786
*4.7K_04
EMI 0
5VS_CRT
PRE: TMDS output driver pre-emphasis level setting,
3 level CMOS input, internal pull-down at ~ 500k ohm
PRE=LOW: No pre-emphasis
PEQ: TMDS iutput equalization control, 3 level CMOS input,
internal pull-down at ~ 500k ohm
PEQ=LOW: Mid level EQ(Default)
PEQ=High: High level EQ
PEQ=MID: Low level EQ
HPDX: Output level and polarity of HPD is defined by PIO
PIO=LOW: HPD=HPD_SINK@3.3V CMOS output
PIO=High: HPD=HPD_SINK#(inverted HPD)@0.9V
PIO: Internal pull down ~ 500k ohm
3.3VS
ASQ1
EMI0
ASQ0
EMI1
APD
DDCBUF
PRE
R777
*4. 7K_04
R776
*4. 7K_04
R778
*4. 7K_04
R779
*4. 7K_04
R780
*4. 7K_04
3.3VS
Summary of Contents for W251EUQ
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