CMT2380F17
Rev0.1 | 192/347
www.cmostek.com
Bit 7~6: DTPS1~0, Clock Pre-Scaler of Dead-Time counter.
DTPS[1:0]
Pre-Scaler
Selection
00
SYSCLK
01
SYSCLK/2
10
SYSCLK/4
11
SYSCLK/8
Bit 5~0: DT5~0, Dead-Time period control bits.
DT[5:0]
Dead-Time Period
000000
Dead-Time Disabled
000001
Pre-Scaler Clock X 1
000010
Pre-Scaler Clock X 2
000011
Pre-Scaler Clock X 3
……
……
111110
Pre-Scaler Clock X 62
111111
Pre-Scaler Clock X 63
PWMCR
：
PWM Control Register
SFR Page
= 0 only
SFR Address = 0xBC
Bit
7
6
5
4
3
2
1
0
Name
PCAE
EXDT
PBKM
PBKE1.1
PBKE1.0
PBKE0.2
PBKE0.1
PBKE0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
0
0
0
Bit 7: PCAE, PWM Central Aligned Enabled. PCAE controls the enabled PWM channels to central
aligned modulation including buffer mode PWM or non-buffer mode PWM. In this PWM mode, the PWM
frequency is the half of edge aligned mode. This function is only active on PWMO0~5.
0: Set the PWM function with edge aligned modulation.
1: Enable the PWM function with central aligned modulation. It only supports 8/10/12/16-bit resolution on
CHRL and CLRL setting.
Bit 6: EXDT: Extend Dead-Time in PWM Period. This function will corrupt the non-PWM channel function.
Such as capture mode, software timer mode and high speed output mode.
0: Disable M + 2P.
1: Enable M + 2P on enabled PWM channel.
Figure 17-16. Waveform of Edge Aligned PWM and Central Aligned PWM
Bit 5: PBKM, PWM Break Mode selection.
0: Latched Mode.
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
