CMT2380F17
Rev0.1 | 64/347
www.cmostek.com
DMADS0: DMA Data path Selection Register 0
SFR Page
= 9 only
SFR Address = 0x94
Bit
7
6
5
4
3
2
1
0
Name
DSS30
DSS20
DSS10
DSS00
DDS30
DDS20
DDS10
DDS00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
0
0
0
Bit 7~4: DMA data Source Selection.
Bit 3~0: DMA data Destination Selection.
DSS30~00
Source Selection
DDS30~00
Destination
Selection
0
0
0
0
Disabled
0
0
0
0
Disabled
0
0
0
1
S0RX
0
0
0
1
S0TX
0
0
1
0
S1RX
0
0
1
0
S1TX
0
1
0
1
TWI0RX
0
1
0
1
TWI0TX
0
1
1
1
SPI0RX
0
1
1
1
SPI0TX
1
0
0
1
ADC0
[1]
1
0
0
1
Reserved
1
1
0
1
Reserved
1
1
0
1
CRC
1
1
1
1
XRAM
1
1
1
1
XRAM
Note 1: When use DMA to transfer ADC data, please watch out the Data Bit setting. Please reference
"Transfer ADC Data by DMA" in ADC Moudle for details.
8.4
Timer5 Register
T5CON: Timer 5 Control Register
SFR Page
= 3 Only
SFR Address = 0xC8
Bit
7
6
5
4
3
2
1
0
Name
TF5
--
T5CKS1
T5CKS0
T5IE
TR5
T5GAT1
T5GAT0
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
0
0
0
Bit 7: TF5, Timer 5 overflow flag.
0: TF5 must be cleared by software.
1: TF5 is set by a Timer 5 overflow happened.
Bit 6: --.
Bit 5~4: T5CKS.1~0, Timer 5 clock source selector.
。
T5CKS.1~0
T5 Clock Selection
00
SYSCLK/12
01
T5 pin
（
P3.4
）
10
SYSCLK
11
T2EXI input selection
Bit 3: T5IE, TF5 interrupt enable.
0: Disable TF5 interrupt.
1: Enable TF5 interrupt to share the DMA interrupt vector.
Bit 2: TR5, Timer 5 Run control bit.
0: Disabled to stop the Timer/Counter 5. Before starting the DMA process, software must be disabled
TR5.
1: Enabled to start the Timer/Counter 5.
Bit 1~0: T5GAT.1~0, Gating source selection of Timer 5.
T5GAT.1~0
T5 Gate source
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
