CMT2380F17
Rev0.1 | 77/347
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CKCON3
: Clock Control Register 3
SFR Page
= P only
SFR Address = 0x41
Bit
7
6
5
4
3
2
1
0
Name
WDTCS[1:0]
FWKP
WDTFS
MCKD1
MCKD0
1
0
R/W
R/W
R/W
W
R/W
R/W
R/W
W
W
Reset Value
0
0
0
0
0
0
1
0
Bit 7~6: WDTCS1~0, WDT Clock Source selection [1:0].
WDTCS1~0
WDT Clock Source
00
ILRCO
01
ECKI(P6.0)
10
SYSCLK/12
11
S0TOF
Bit 4: WDTFS. WDT overflow source selection.
0: Select WDT bit-8 overflow as WDT event source.
1: Select WDT bit-0 overflow as WDT event source.
PCON1
: Power Control Register 1
SFR Page
= 0~F & P
SFR Address = 0x97
Bit
7
6
5
4
3
2
1
0
Name
SWRF
EXRF
--
RTCF
--
BOF1
BOF0
WDTF
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
W
Reset Value
0
0
0
0
X
0
0
0
Bit 1: WDTF, WDT overflow flag.
0: This bit
must be cleared by software writing “1” on it. Software writing “0” is no operation.
1: This bit is only set by hardware when WDT overflows. Writing “1” on this bit will clear WDTF.
SFIE
: System Flag Interrupt Enable Register
SFR Page
= 0~F
SFR Address = 0x8E
Bit
7
6
5
4
3
2
1
0
Name
SIDFIE
--
--
RTCFIE
--
BOF1IE
BOF0IE
WDTFIE
R/W
R/W
W
W
R/W
W
R/W
R/W
R/W
Reset Value
0
0
0
0
X
0
0
0
Bit 0: WDTFIE, Enable WDTF (PCON1.0) Interrupt.
0: Disable WDTF interrupt.
1: Enable WDTF interrupt.
10.4
WDT Hardware Option
In addition to being initialized by software, the WDTCR register can also be automatically initialized at
power-up by the hardware options WRENO, NSWDT, HWENW, HWWIDL and HWPS[2:0], which should be
programmed by a universal Writer or Programmer, as described below.
If HWENW is programmed to “enabled”, then hardware will automatically do the following initialization for
the WDTCR register at power-up:
(1) set ENW bit;
(2) load WRENO into WREN bit;
(3) load NSWDT into NSW bit;
(4) load HWWIDL into WIDL bit;
(5) load HWPS[2:0] into PS[2:0] bits.
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
