4-30
Service Manual
4.6
Console Halt Conditions
Double error halts are conditions in which the processing of a fatal
error triggers a second error. The TL6 Machine Check 670/660 logout
frame provides error information to the operating system error
handler.
4.6.1
CPU Double Error Halt
The CPU double error halt is caused by two conditions:
1.
The machine is processing a Machine Check and trapping back into the
Machine Check prior to exiting the first machine check. The operating
system clears MCES MCHK in Progress bit to signal exiting the handler.
2.
While PALcode is executing, the machine tries to enter a Machine Check,
thus causing a Double Error halt.
Under both of these conditions continuing system operation is not possible and
the machine state cannot be saved under normal mechanism, such as error
logging. For these conditions, PAL and the console save the appropriate state
information in EEPROM.
When the system is booted, if any double halt error
logs exist in the EEPROM, the halt data is copied from the EEPROM into
memory. A pointer, in the per-CPU Slot area of the HWRPB indicates the
memory location of the halt data. Using this pointer, the double error halt
information is written into the error log.
