CDD-562AL/564A/L Multi-Channel Demodulator
Revision 0
Introduction
MN-CDD562AL/564AL
1–3
A/D converter. An AGC circuit controls the signal level presented to the A/D converter. Digital signal
processing does the final quadrature conversion to baseband, followed by Nyquist filtering, carrier
recovery and symbol timing recovery. The resulting demodulated signal is fed, in soft decision form, to
the selected FEC decoder. The FEC decoder can be TPC or VersaFEC.
After decoding, the recovered clock and data pass to the IP Module. In the IP Module, traffic is examined
and processed for four channels before it is delivered to the Ethernet port.
The demodulator’s signal processing functions occur in two, large Field-Programmable Gate Arrays
(FPGA). This permits rapid implementation of changes, additions and enhancements in the field. These
signal-processing functions are controlled and monitored by a 32-bit RISC microprocessor, which also
controls serial and Ethernet interfaces.
As shown in the block diagrams in
Figure 1-3
, the demodulator is comprised of a single printed circuit
board assembly with integral FEC and IP router.
Summary of Contents for CDD-562AL
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