2.0 Functional Description
Fusion 878A
2.12 DMA Controller
PCI Video Decoder
2-46
Conexant
100600B
The planar mode requires that the DMA controller give priority to the Y FIFO
to be emptied first. If there is a very long latency in getting access to the PCI bus,
all three FIFOs will be almost full when the bus is finally granted. While bursting
the Y data, the CrCb data is likely to overflow. Attempting to deliver data from
each FIFO to the bus will yield poor bus performance. Preference is given to the
Y FIFO to finish the burst write operation, and if Cr or Cb FIFOs each reach a
full condition, the DMA controller will discard their data in parallel to delivering
the Y data.
2.12.7 FIFO Data Stream Resynchronization
The Fusion 878A DMA controller is constantly monitoring whether there is a
mismatch between the amount of data expected by the RISC instruction and the
amount of data being provided by the FIFO. The DMA controller then corrects
for the mismatches and realigns the RISC program and the FIFO data stream.
For example, if the FIFO contains a shorter video line than expected by the
RISC instruction, the DMA controller detects the EOL control code from the
FIFO earlier than expected. The DMA controller then aborts the rest of the RISC
instructions until it detects the EOL control code from the RISC program.
If the FIFO contains a longer video line than expected by the RISC
instruction, the DMA controller will not detect the EOL control code from the
FIFO at the expected time. The DMA controller will continue reading the FIFO
data; however it will discard the additional FIFO data until it reaches the EOL
control code from the FIFO.
Similarly, if the FIFO provides a smaller number of scan lines per field than
expected by the RISC program, the end of field control codes from the FIFO
(VRE/VRO) will arrive early. The DMA controller then aborts all RISC
instructions until the SYNC status codes from the RISC instruction match the end
of field status codes from the FIFO.
If the FIFO provides a larger number of scan lines per field than expected by
the RISC program, the end of field control codes from the FIFO (VRE/VRO) will
not arrive at the expected time. Again, the FIFO data is read by the DMA
controller and discarded until the SYNC status codes from the RISC instruction
match the end of field status codes from the FIFO.
The DMA controller manages all of the above error conditions, but the FIFO
Data Stream Resynchronization (FDSR) interrupt bit will be set as well.
