7.1 X1 Connector Signal Descriptions
Table 3
Signal Descriptions
Signal
Description
I/O
PU/PD
Comment
VCC
Power 5VDC ±5%
P
External supply
GND
Power Ground
P
External supply
3V
Power 3.3VDC
P
See section 4.1.4
N.C.
Not Connected
N.A.
Do not connect
SERIRQ
Serial Interrupt request
I 3.3V
PU 10K 3.3V
Table 4
PCI Signal Descriptions
Signal
Description of PCI Bus
Signals
I/O
PU/PD
Comment
PCICLK1..4.
Clock output
O 3.3V
REQ0..3#
Bus request
I 3.3V
PU 8k2 3.3V
REQ1..3# is a boot strap signal (see
note below) 5V Tolerant
GNT0..3#
Bus grant
O 3.3V
GNT2/3# is a boot strap signal (see
note below)
AD0..31
Address/Data bus lines
I/O 3.3V
5V Tolerant
CBE0..3#
Bus command/byte enables
I/O 3.3V
5V Tolerant
PAR
Bus parity
I/O 3.3V
5V Tolerant
SERR#
Bus system error
I/O 3.3V
PU 8k2 3.3V
5V Tolerant
GPERR#
Bus grant parity error
I/O 3.3V
PU 8k2 3.3V
5V Tolerant
PME#
Bus power management event I/O 3.3VSB PU 10k 3.3VSB
LOCK#
Bus lock
I/O 3.3V
PU 8k2 3.3V
5V Tolerant
DEVSEL#
Bus device select
I/O 3.3V
PU 8k2 3.3V
5V Tolerant
TRDY#
Bus target ready
I/O 3.3V
PU 8k2 3.3V
5V Tolerant
IRDY#
Bus initiator ready
I/O 3.3V
PU 8k2 3.3V
5V Tolerant
STOP#
Bus stop
I/O 3.3V
PU 8k2 3.3V
5V Tolerant
FRAME#
Bus frame
I/O 3.3V
PU 8k2 3.3V
5V Tolerant
PCIRST#
Bus reset
O 3.3V
Asserted during system reset
INTA#
Bus interrupt A
I 3.3V
PU 8k2 3.3V
5V Tolerant
INTB#
Bus interrupt B
I 3.3V
PU 8k2 3.3V
5V Tolerant
INTC#
Bus interrupt C
I 3.3V
PU 8k2 3.3V
5V Tolerant
INTD#
Bus interrupt D
I 3.3V
PU 8k2 3.3V
5V Tolerant
Note
Some signals have special functionality during the reset process. They may bootstrap
some basic important functions of the module. For more information refer to section 7.9
of this user's guide.
Copyright © 2006 congatec AG
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