6. About Hardware
78
AD12-64(PCI), AD12-16(PCI)
Timing for Control Signal
Figures 6.2 and Table 6.2 shows the timing for external sampling clock.
Figure 6.2. Timing for External Sampling Clock
Table 6.2. Description
Parameter
Symbol Time(nsec)
External sampling clock signal falling setup time
tSFS
100nsec
External sampling clock signal falling hold time
tHFS
100nsec
Delay from the fall of external sampling clock signal to the AD
conversion start pulse of the first channel
tDEC
200nsec
All of the times in Table 6.2 are typical values.
t
SFS
t
HFS
t
DEC
External Sampling Clock
Conversion Start
CAUTION
