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C
URTISS
-W
RIGHT
L
IST
OF
F
IGURES
826448 V
ERSION
5 M
ARCH
2015
P
ROPRIETARY
IX
L
IST
OF
F
IGURES
Figure 1.1:
Air-Cooled CHAMP-AV8 Isometric View...............................................................................1-3
Figure 1.2:
CHAMP-AV8 Functional Block Diagram ...............................................................................1-5
Figure 1.3:
CHAMP-AV8 PCI Express Distribution .................................................................................1-7
Figure 1.4:
PCIe Switch Partitions......................................................................................................1-9
Figure 1.5:
CHAMP-AV8 SRIO Port Connections .................................................................................1-11
Figure 1.6:
Core Functions FPGA Block Diagram ................................................................................1-12
Figure 1.7:
Boot Flash SPI Bus Architecture ......................................................................................1-14
Figure 1.8:
CHAMP-AV8 Serial Port Implementation ...........................................................................1-18
Figure 1.9:
CHAMP-AV8 Serial Port Detail .........................................................................................1-19
Figure 1.10:
Location of Voltage, Current, and Temperature Sensors (Primary Side) ................................1-22
Figure 1.11:
Location of Voltage, Current, and Temperature Sensors (Secondary Side) ............................1-23
Figure 1.12:
CHAMP-AV8 Interrupt Controller Block Diagram ................................................................1-25
Figure 1.13:
Interrupt Routing Block (Part A)......................................................................................1-28
Figure 1.14:
Interrupt Routing Block (Part B)......................................................................................1-29
Figure 1.15:
CHAMP-AV8 Board Layout—Primary Side) ........................................................................1-35
Figure 1.16:
CHAMP-AV8 Board Layout—Secondary Side ......................................................................1-36
Figure 1.17:
Status LEDS on Conduction-Cooled Variants .....................................................................1-38
Figure 2.1:
CBL-462-FPL-000 (CHAMP-AV8 Standard Front Panel Cable Assembly)...................................2-6
Figure 2.2:
Configuration Jumper Locations ........................................................................................2-8
Figure 3.1:
Location of CHAMP-AV8 Ethernet Activity LEDs....................................................................3-7
Figure 3.2:
System Boot Screen ......................................................................................................3-11
Figure 3.3:
GRUB Loading Message..................................................................................................3-13
Figure A.1:
VPX System Connectors Overview .................................................................................... A-3
Figure A.2:
VPX RT2 Type Connector................................................................................................. A-4
Figure A.3:
VPX RT2 Wafer Routings ................................................................................................. A-5
Figure A.4:
CHAMP-AV8 Backplane P0-P6 Connector Orientation ........................................................... A-7
Figure A.5:
I/O Mapping to the CHAMP-AV8 VITA 46 Connectors........................................................... A-8
Figure A.6:
CHAMP-AV8 Pinout Configurator Main Window ..................................................................A-11
Figure A.7:
Sample P5 Pinout Table .................................................................................................A-12
Figure A.8:
CHAMP-AV8 P0 Utility Connector .....................................................................................A-14
Figure A.9:
CHAMP-AV8 P1 SRIO Fabric Connector.............................................................................A-17
Figure A.10:
CHAMP-AV8 VITA 46 P2 Connector ..................................................................................A-20
Figure A.11:
P3 XMC Site’s PMC User I/O Connector ............................................................................A-23
Figure A.12:
P4 Basecard I/O Connector.............................................................................................A-26
Figure A.13:
P5 XMC User I/O Connector............................................................................................A-30
Figure A.14:
P6 XMC/DIO/PCIe Connector ..........................................................................................A-33
Figure A.15:
J1 Contact Numbering Arrangement (Looking into the Front Panel) ......................................A-38
Figure A.16:
Location of CHAMP-AV8 J14 Connector.............................................................................A-39
Figure A.17:
Location of CHAMP-AV8 XMC J15 and J16 Connectors ........................................................A-42
Figure A.18:
CHAMP-AV8 Rear Transition Module Views........................................................................A-52
Figure A.19:
RTM Printed Wiring Board Component Side View ...............................................................A-53
Figure A.20:
Serial Port Loopback Control via RTM P3 ..........................................................................A-55
Figure A.21:
Proper Jumper Orientation for RTM P3 Jumpers .................................................................A-56
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