C
URTISS
-W
RIGHT
1
826448 V
ERSION
5 M
ARCH
2015
P
ROPRIETARY
A-31
Table A.18:
P5 XMC User I/O Connector Pin Assignments
Wafer
No.
Row G
Signal
Row F
Signal
Row E
Signal
Row D
Signal
Row C
Signal
Row B
Signal
Row A
Signal
1
NC
GND
NC
NC
GND
NC
NC
2
GND
NC
NC
GND
NC
NC
GND
3
NC
GND
NC
NC
GND
XMC_C01
XMC_F01
4
GND
XMC_C02
XMC_C03
GND
XMC_F02
XMC_F03
GND
5
NC
GND
XMC_C04
XMC_C05
GND
XMC_F04
XMC_F05
6
GND
XMC_C06
XMC_C07
GND
XMC_F06
XMC_F07
GND
7
NC
GND
XMC_C08
XMC_C09
GND
XMC_F08
XMC_F09
8
GND
XMC_C10
XMC_C11
GND
XMC_F10
XMC_F11
GND
9
NC
GND
XMC_C12
XMC_C13
GND
XMC_F12
XMC_F13
10
GND
XMC_C14
XMC_C15
GND
XMC_F14
XMC_F15
GND
11
NC
GND
XMC_C16
XMC_C17
GND
XMC_F16
XMC_F17
12
GND
XMC_C18
XMC_C19
GND
XMC_F18
XMC_F19
GND
13
NC
GND
XMC_A1
XMC_B1
GND
XMC_D1
XMC_E1
14
GND
XMC_A3
XMC_B3
GND
XMC_D3
XMC_E3
GND
15
NC
GND
XMC_A11
XMC_B11
GND
XMC_D11
XMC_E11
16
GND
XMC_A13
XMC_B13
GND
XMC_D13
XMC_E13
GND
Table A.19:
P5 XMC User I/O Connector Signal Definitions
CHAMP-AV8 Signal
Description
XMC_C[19:01]
XMC_F[19:01]
XMC Single-Ended User I/O Mapping from XMC J16 connector (38 single ended signals).
These connection supports high-speed single-ended signals.
XMC_DP[3:0]_P
XMC_DP[3:0]_N
XMC_DP[13:10]_P
XMC_DP[13:10]_N
XMC Differential User I/O Mapping from XMC J16 connector to V46 P5 connector (8 pairs).
Mapped in accordance with V46.9, P5w3P6-X38s+X8d+X12d pattern.
NC
No Connect
GND
Ground signals as defined in VITA 46.0.
Note
Electrical characteristics of XMC signals are determined by the XMC module used. Please
consult the XMC module User's Manual for exact details.
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