CHAMP-AV8 (VPX6-462) H
ARDWARE
U
SER
’
S
M
ANUAL
C
URTISS
-W
RIGHT
1-30
P
ROPRIETARY
826448 V
ERSION
5 M
ARCH
2015
Interrupt
Messaging FIFO
Each enabled interrupt event for IRQ0-1 will generate a message vector which will be stored
in the interrupt message FIFO. There is a separate FIFO for each IRQ. Only edge-mode
interrupts are supported, and software must ensure that only edge-mode interrupts are
routed to these IRQs. Anytime an enabled interrupt occurs, it will send a single message into
the message FIFO. The message indicates that "interrupt X has occurred". The CPU will be
able to read the message to determine which interrupt occurred, which is much faster than
having to read multiple interrupt status registers.
Serial IRQ
Interface
Of the thirteen IRQ outputs from the routing/control block, IRQ0-4 will be sent to the PCH
using a serial IRQ scheme. In addition, SRC16 (8 bits wide) are also sent to PCH over the serial
IRQ. This allows a single signal to be used to report interrupt requests to the CPU. The signal
used to transmit this information is shared between the PCH and all peripherals that support
serial interrupts. The signal line, SERIRQ, is synchronous to the PCI clock, and follows the
sustained tri-state protocol that is used by all PCI signals.
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