C
URTISS
-W
RIGHT
P
RODUCT
O
VERVIEW
826448 V
ERSION
5 M
ARCH
2015
P
ROPRIETARY
1-35
P
HYSICAL
C
HARACTERISTICS
Figure 1.15 shows the location of the major components and the mating connectors on the
top side of the CHAMP-AV8 (some hardware has been removed from this drawing to make all
of the components visible).
All ruggedization levels of the CHAMP-AV8 board have a thermal shunt that covers some of
the components.
Figure 1.15: CHAMP-AV8 Board Layout—Primary Side)
Node A
Processor
U1
Node B
Processor
U2
SRIO
Switch
U84
Node A
PCH
U3
Node B
PCH
U4
PCIe
Switch
U128
Common
Features
FPGA
Memory
Mezzanine
Connector
Memory
Mezzanine
Connector
Memory
Mezzanine
Connector
Memory
Mezzanine
Connector
P0
P1
P2
P3
P4
P5
P6
CPLD
XMC J15
XMC J16
Ethernet
XMC J14
PCIe-
SRIO
PCIe-
SRIO
PCIe-
SRIO
PCIe-
SRIO
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